Renesas M16C/60 Series Hardware Manual page 271

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M16C/6N5 Group
Memory Expansion Mode and Microprocessor Mode
(
For 3-wait setting, external area access and multiplexed bus selection
Read timing
BCLK
CSi
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
ADi
/DB
t
d(BCLK-AD)
25ns.max
ADi
BHE
(no multiplex)
t
d(BCLK-ALE)
25ns.max
ALE
RD
Write timing
BCLK
CSi
ADi
/DB
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
(no multiplex)
t
d(BCLK-ALE)
25ns.max
ALE
WR, WRL
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
V = 5 V
CC
Input timing voltage : V
Output timing voltage : V
Figure 1.21.9 Timing Diagram (8)
Rev.1.00 2003.05.30 page 257
tcyc
t
d(BCLK-CS)
25ns.max
t
h(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
Address
t
dZ(RD-AD)
t
8ns.max
d(AD-RD)
(2.5 ✕ tcyc-45)ns.max
0ns.min
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
tcyc
t
d(BCLK-CS)
25ns.max
t
d(BCLK-DB)
40ns.max
Address
t
h(BCLK-ALE)
-4ns.min
t
d(AD-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
= 0.8 V, V = 2.0 V
IL IH
= 0.4 V, V = 2.4 V
OL OH
)
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
Data input
t
ac3(RD-DB)
t
SU(DB-RD)
40ns.min
(0.5 ✕ tcyc-10)ns.min
Data output
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
Electrical Characteristics
t
h(BCLK-CS)
4ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-RD)
0ns.min
t
h(BCLK-CS)
t
h(WR-CS)
4ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min