Renesas M16C/60 Series Hardware Manual page 154

Under development
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M16C/6N5 Group
UARTi special mode register 2 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
UARTi special mode register 3 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I
mode, set these bits to "000
Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
Figure 1.15.7 U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
Rev.1.00 2003.05.30 page 140
Symbol
U0SMR2 to U2SMR2 01EE
Bit
Bit name
symbol
2
IICM2
I C mode select bit 2
CSC Clock-synchronous bit
SCL wait output bit
SWC
ALS SDA output stop bit
STAC UARTi initialization bit
SCL wait output bit 2
SWC2
SDHI
SDA output disable bit
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is indeterminate.
Symbol
U0SMR3 to U2SMR3 01ED
Bit
Bit name
symbol
Nothing is assigned When write, set to "0". .
(b0)
When read, its content is indeterminate.
CKPH Clock phase set bit
Nothing is assigned. When write, set to "0".
(b2)
When read, its content is indeterminate.
NODC Clock output select bit
Nothing is assigned. When write, set to "0".
(b4)
When read, its content is indeterminate.
DL0
SDAi digital delay
DL1
setup bit
(Notes 1, 2)
DL2
" (no delay).
2
Address After reset
, 01F2 , 01F6 X0000000
16 16 16
Function
2
Refer to "Table 1.15.11 I C Mode FUnctions"
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0: Transfer clock
1: "L" output
0: Enabled
1: Disabled (high-impedance)
Address After reset
, 01F1 , 01F5 000X0X0X
16 16 16
Function
0 : Without clock delay
1 : With clock delay
0 : CLKi is CMOS output
1 : CLKi is N channel open-drain output
b7 b6 b5
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Serial I/O
2
RW
RW
RW
RW
RW
RW
RW
RW
2
RW
RW
RW
RW
RW
RW
2 C mode. In other than I 2 C