Renesas M16C/60 Series Hardware Manual page 160

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M16C/6N5 Group
(a) CLK Polarity Select Function
Use the UiC0 register (i = 0 to 2)'s CKPOL bit to select the transfer clock polarity. Figure 1.15.10
shows the polarity of the transfer clock.
(1) When the UiC0 register's CKPOL bit = 0 (transmit data output at the falling
CLK
T
X
R X
(2) When the UiC0 register's CKPOL bit = 1 (transmit data output at the rising
CLK
T
X
R
X
i = 0 to 2
* This applies to the case where the UiC0 register's UFORM bit = 0
(LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).
Note 1: When not transferring, the CLKi pin outputs a high signal.
Note 2: When not transferring, the CLKi pin outputs a low signal.
Figure 1.15.10 Transfer Clock Polarity
(b) LSB First/MSB First Select Function
Use the UiC0 register (i = 0 to 2)'s UFORM bit to select the transfer format. Figure 1.15.11 shows the
transfer format.
Figure 1.15.11 Transfer Format
Rev.1.00 2003.05.30 page 146
edge and the receive data taken in at the rising edge of the transfer clock)
i
D0 D D
D 1 2
i
D D D
0 1 2
D i
edge and the receive data taken in at the falling edge of the transfer clock)
i
D D D
D 0 1 2
i
D D D
D 0 1 2
i
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLK
i
D0 D
T D 1
X i
D
D 1
R D 0
X i
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLK
i
D D
T D 7 6
X i
D D
R D 7 6
X i
i = 0 to 2
* This applies to the case where the UiC0 register's CKPOL bit = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register's
UiLCH bit = 0 (no reverse).
Serial I/O (Clock Synchronous Serial I/O Mode)
D D D D D
3 4 5 6 7
D D D D D
3 4 5 6 7
D D D D D
3 4 5 6 7
D D D D D
3 4 5 6 7
D D D D D
2 3 4 5 6
D D D D D
2 3 4 5 6
D D D D D
5 4 3 2 1
D D D D D
5 4 3 2 1
(Note 1)
(Note 2)
D
7
D
7
D
0
D
0