The Rdy Signal - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group
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(6) The RDY Signal

This signal is provided for accessing external devices which need to be accessed at low speed. If input on
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the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in
the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.
A to A , D to D
0 19 0 15
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 1.7.4 shows example in which the wait state was inserted into the read cycle by the
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RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register
to "0" (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.
In an instance of separate bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
In an instance of multiplexed bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
t
SU(RDY-BCLK)
Shown above is the case where CSEi1W to CSEi0W (i = 0 to 3) bits in the CSE register are
"00 " (one wait state).
2
Figure 1.7.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal
Rev.1.00 2003.05.30 page 35
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, CS to CS , RD, WRL, WRH, WR, BHE, ALE, HLDA
0 3
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t
su(RDY - BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
: RDY input setup time
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t
su(RDY - BCLK)
Accept timing of RDY signal
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Bus Control
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