Renesas M16C/60 Series Hardware Manual page 61

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
Peripheral clock select register (Note)
b7 b6 b5 b4 b3 b2
0 0 0 0 0 0
Note: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Figure 1.8.5 PCLKR Register
CAN0 clock select register (Notes 1, 2)
b7 b6 b5 b4 b3 b2
1 0 0 0
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: Configuration of this register can be done only when the Reset bit of C0CTLR register = 1 (Reset/Initialization
mode).
Figure 1.8.6 CCLKR Register
Rev.1.00 2003.05.30 page 47
b1 b0
Symbol
PCLKR
Bit symbol
Timers A, B, and A-D clock select bit
PCLK0 (Clock source for the timers A, B,
the dead time timer and A-D)
SI/O clock select bit
(Clock source for UART0 to
PCLK1
UART2, SI/O3)
-
Reserved bit
(b7-b2)
b1 b0
Symbol
CCLKR
Bit symbol
CCLK0
CAN0 clock select bits
CCLK1
CCLK2
CAN0 CPU interface
CCLK3
sleep bit
-
Reserved bit
(b6-b4)
-
Reserved bit
(b7)
Address After reset
025E 00
16 16
Bit name
0 : Divide-by-2 of f
1 : f
0 : f
1 : f
Set to
Address After reset
025F 00
16 16
Bit name
b2 b1 b0
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
1 0 0: Divide-by-16
1 0 1 :
1 1 0 :
1 1 1 :
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
"0"
Set to
"1"
Set to
Clock Generation Circuit
Function
RW
, f
AD2 2
, f
AD 1 RW
2SIO
RW
1SIO
"0"
RW
Function
RW
RW
RW
Inhibited
RW
RW
RW
RW