Watchdog Timer - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

Watchdog Timer

The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend
using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter
which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a
watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the
watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit of PM1
register. The PM12 bit can only be set to "1" (watchdog timer reset). Once this bit is set to "1", it cannot be
set to "0" (watchdog timer interrupt) in a program. Refer to "Watchdog Timer Reset" for details about watchdog
timer reset.
When the main clock is selected for CPU clock, ring oscillator clock, PLL clock, the divide-by-n value for the
prescaler can be selected to be 16 or 128. If a sub clock is selected for CPU clock, the divide-by-n value for
the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calcu-
lated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler.
With main clock selected for CPU clock, ring oscillator clock, PLL clock
Watchdog timer period =
With sub clock selected for CPU clock
Watchdog timer period =
For example, when CPU clock = 16 MHz and the divide-by-n value for the prescaler = 16, the watchdog timer
period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released.
Figure 1.11.1 shows the block diagram of the watchdog timer. Figure 1.11.2 shows the watchdog timer-
related registers.
• Count source protective mode
In this mode, a ring oscillator clock is used for the watchdog timer count source. The watchdog timer can
be kept being clocked even when CPU clock stops as a result of runaway.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit of the PRCR register to "1" (enable writes to the PM1 and PM2 registers).
(2) Set the PM12 bit of the PM1 register to "1" (reset when the watchdog timer underflows).
(3) Set the PM22 bit of the PM2 register to "1" (ring oscillator clock used for the watchdog timer count source).
(4) Set the PRC1 bit of the PRCR register to "0" (disable writes to the PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Rev.1.00 2003.05.30 page 85
Prescaler dividing (16 or 128) ✕ Watchdog timer count (32768)
Prescaler dividing (2) ✕ Watchdog timer count (32768)
CPU clock
CPU clock
Watchdog Timer