Clock Stop Register 2 (Ckstpr2) - Renesas H8 Series Hardware Manual

11.2.3

Clock Stop Register 2 (CKSTPR2)

Bit 7
LVDCKSTP *
Initial value 1
Read/Write
R/W
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the PWM is described here. For details of the other bits, see the
sections on the relevant modules.
Bits 4 and 1—PWM Module Standby Mode Control (PWmCKSTP)
Bits 4 and 1 control setting and clearing of module standby mode for the PWMm.
PWmCKSTP Description
0 PWMm is set to module standby mode
1 PWMm module standby mode is cleared
6 5
— — PW2CKSTP AECKSTP
1 1
R/W
— —
4 3 2
WDCKSTP PW1CKSTP LDCKSTP
1 1 1
R/W R/W
Rev. 7.00 Mar 10, 2005 page 395 of 652
Section 11 10-Bit PWM
1 0
1 1
R/W R/W
(initial value)
REJ09B0042-0700