Serial Control Register 3 (Scr3) - Renesas H8 Series Hardware Manual

Section 10 Serial Communication Interface
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see section
10.2.8, Bit rate register (BRR).
Bit 1 Bit 0
CKS1 CKS0
0 0
0 1
1 0
1 1
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode. In subactive or subsleep mode, SCI3
can be operated when CPU clock is φw/2 only.
10.2.6

Serial Control Register 3 (SCR3)

Bit 7
TIE
Initial value 0
Read/Write R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, module standby or watch mode.
Bit 7—Transmit Interrupt Enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Rev. 7.00 Mar 10, 2005 page 340 of 652
REJ09B0042-0700
Description
φ clock
φ w/2 clock *
1
/φ w clock *
φ/16 clock
φ/64 clock
6 5
RIE TE
0 0
R/W R/W
2
4 3
RE MPIE
0 0
R/W R/W
(initial value)
2 1
TEIE CKE1 CKE0
0 0
R/W R/W R/W
0
0