Serial Control Register 3 (Scr3) - Renesas H8/36912 Series User Manual

Bit Bit Name
1 CKS1
0 CKS0
14.3.6

Serial Control Register 3 (SCR3)

SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7,
Interrupts.
Bit Bit Name
7 TIE
6 RIE
5 TE
4 RE
3 MPIE
Rev. 1.00, 11/03, page 192 of 376
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Initial
Value R/W Description
0 R/W Clock Select 0 and 1
0 R/W These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 14.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n in
BRR (see section 14.3.8, Bit Rate Register (BRR)).
Initial
Value R/W Description
0 R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
0 R/W Transmit Enable
When this bit s set to 1, transmission is enabled.
0 R/W Receive Enable
When this bit is set to 1, reception is enabled.
0 R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, refer to section 14.6, Multiprocessor
Communication Function.