Status Register (Ssr0-3) - Fujitsu MB91150 Series Hardware Manual

CHAPTER 15 UART

15.4.3 Status register (SSR0-3)

The status register (SSR0-3) is used to check the send, receive and error statuses, and
sets interrupt enabled or disabled.
I Status register (SSR0-4)
The configuration of the status register (SSR0-3) is shown below.
Address
ch0:0000_001Ch
ch1:0000_0020h
ch2:0000_0024h
ch3:0000_0028h
R/W: Read/write enabled
R: Read only
TIE
Send-interrupt request enable bit
0
Disables send-interrupt request output
1
Enables send-interrupt request output
RIE Receive-interrupt request enable bit
0
Disables receive-interrupt request output
1
Enables receive-interrupt request output
Transfer direction selection bit
BDS
0
LSB first (transfer begins from the least significant bit)
1
MSB first (transfer begins from the most significant bit)
TDRE Send data empty flag bit
With send data (disables send data to be written)
0
Without send data (enables send data to be written)
1
0 , 1 : The underline indicates an initial value.
[Bit 15] PE (Parity error flag bit)
• If a parity error occurs at reception, this bit is set to 1. When the REC bit of the mode register
(SMR0-4) is set to 0, this bit is cleared.
• When this bit and the RIE bit are 1, a receive-interrupt request is output.
• When this flag is set, data in the input-data register (SIDR0-3) is invalid.
316
Figure 15.4-4 Status register (SSR0-3)
bit15 bit14 bit13 bit12
PE ORE FRE RDRF
R R R
bit11 bit10 bit9
TDRE BDS RIE
R R R/W R/W
RDRF
0
1
FRE
0
1
ORE
0
1
PE
0
1
bit8 bit7 ............... bit0
TIE (SIDR/SODR)
R/W
Initial value
00001000
B
Receive data full flag bit
Without receive data
With receive data
Framing error flag bit
Without framing error
With framing error
Overrun error flag bit
Without overrun error
With overrun error
Parity error flag bit
Without parity error
With parity error