Counter Status Register 0/1 (Csr0/1) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER

13.2.4 Counter status register 0/1 (CSR0/1)

This section describes the configuration and explains the function of counter status
register 0/1 (CSR0/1).
I Counter status register 0/1 (CSR0/1)
The bit configuration of the counter status register 0/1 (CSR0/1) is shown below.
Figure 13.2-5 Bit configuration of counter status register 0/1(CSR0/1)
Bit
CSR0
Address: 000072
CSR 1
Address: 000074
Counter status register 0/1 (CSR0/1) consists of bits that have the functions explained below.
[Bit 7] CSTR (count start)
This bit is used to control the UDCR count start/stop operation.
CSTR
0
1
[Bit 6] CITE (compare interrupt output control)
This bit is used to control permit/prohibit of interrupt output to the CPU if CMPF is defined (if
a compare occurs).
CITE
0
1
[Bit 5] UDIE (overflow/underflow interrupt output control)
This bit is used to control the permit/prohibit of interrupt output to the CPU if OVFF/UDFF is
defined (if overflow/underflow occurs).
UDIE
0
1
260
7 6 5
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
H
R/W R/W R/W R/W R/W
H
Count start/stop operation
Count operation stop (initial value)
Count operation start
Permit/prohibit of compare interrupt output
Compare interrupt output prohibited (initial value)
Compare interrupt output permitted
Permit/prohibit of overflow/underflow interrupt output
Overflow/underflow interrupt output prohibited (initial value)
Overflow/underflow interrupt output permitted
4 3 2 1
R/W R
0 Initial value
00000000
B
R