Flag & Status Register - Fujitsu MB86617A Specification Sheet

LSI S pecification
7.2. flag & status Register
flag & status register indicates the status of this LSI and data access inquiries.
Bit Bit
AD R/W
15 14
IPC tran
02h R
busy ready
Initial Value '0' '0'
BIT Bit Name
15 IPC busy
14 tran ready
13 tran busy
12 ISO cycle
A-T x-buff
11
Empty
A-Rx-buff
10
Empty
9 – 5 reserved
Rev.1.0
Bit Bit Bit Bit
13 12 11 10
A-Tx- A-Rx-
tran ISO
buff buff
busy cycle
empty empty
'0' '0' '1' '1'
Action Value
0 Indicates that receipt of instruction is available.
Read
1 Indicates that receipt of instruction is not available.
Indicates that bus reset or forced sleep is being executed, and transmit/receive of
0
packet is unavailable.
Read
Indicates that bus reset is completed and forced sleep is not being executed, and
1
transmit/receive of packet is available.
Indicates that packet transmit is not being executed or in the process of packet
0
receive addressed to this node.
Read
Indicates that packet transmit is being executed or in the process of packet receive
1
addressed to this node.
0 Indicates that Isochronous cycle is not being executed.
Read
Indicates that Isochronous cycle is being executed by transmit or receive of cycle
1
start packet.
0 Indicates that Asynchronous transmit specific buffer is not empty.
Read
1 Indicates that Asynchronous transmit specific buffer is empty.
0 Indicates that Asynchronous receive specific buffer is not empty.
Read
1 Indicates that Asynchronous receive specific buffer is empty.
Read 0 Always indicate '0'.
Bit Bit Bit Bit
9 8 7 6
- - - -
'0' '0' '0' '0'
Function
29
MB86617A
Bit Bit Bit Bit
5 4 3 2
data recv
sleep
-
req busy
'0' '0' '0' '0'
Fujitsu VLSI
Bit Bit
1 0
cmstr INT
'0' '0'