Data Flash Control Register (Dflashctrl); Data Flash Control Register (Dflashctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

DEC – Address Manager Registers Reference

15.2.21 Data Flash Control Register (DFLASHCTRL)

Address FFFFFE94
11 10 9
BUSY Reserved PAGE_
ERASE
R-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-30. Data Flash Control Register (DFLASHCTRL) Register Field Descriptions
Bit Field
11 BUSY
10 Reserved
9 PAGE_ERASE
8 MASS_ERASE
7-6 Reserved
5-0 PAGE_SEL
494
Memory
Figure 15-25. Data Flash Control Register (DFLASHCTRL)
8 7
MASS_ Reserved
ERASE
R/W-0 R-0
Type Reset
R 0
Data Flash Busy Indicator
0 = Data Flash available for read/write/erase access
1 = Data Flash unavailable for read/write/erase access
R 0
R/W 0
Data Flash Page Erase Enable
0 = No Page Erase initiated on Data Flash (Default)
1 = Page Erase Cycle on Data Flash enabled. Page erased is based on PAGE_SEL
(Bits 4-0). This bit is cleared upon completion of Page Erase cycle.
R/W 0
Data Flash Mass Erase Enable
0 = No Mass Erase initiated on Data Flash (Default)
1 = Mass Erase of Data Flash enabled. Bit is cleared upon completion of mass
erase.
R 0
R/W 000000
Selects page to be erased during Page Erase Cycle
Copyright © 2016, Texas Instruments Incorporated
6 5
Description
SNIU028A – February 2016 – Revised April 2016
www.ti.com
PAGE_SEL
R/W-000000
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