Texas Instruments UCD3138 Technical Reference Manual page 10

10.4.1 Using Early TXBUF Write to Avoid Clock Stretch
10.4.2 Alert Response
10.5 PMBus Slave Mode Low Level Timing
10.6 Effect of MAN_SLAVE_ACK bit on EOM Handling
10.7 Master Mode Operation Reference
10.7.1 Quick Command
10.7.2 Send Byte
10.7.3 Receive Byte
10.7.4 Write Byte/Word
10.7.5 Read Byte/Read Word
10.7.6 Process Call
10.7.7 Block Write
10.7.8 Block Read
10.7.9 Block Write-Block Read Process Call
10.7.10 Alert Response
10.7.11 Extended Command - Write Byte/Word, Read Byte/Word
10.7.12 Group Command
10.8 PMBUS Communications Fault Handling
10.8.1 Bit Counter
10.8.2 Test Mode (Manufacturer Reserved Address Match)
10.9 Other Functions of the PMBus Module
10.10 PMBus Interface Registers Reference
10.10.1 PMBUS Control Register 1 (PMBCTRL1)
10.10.2 PMBus Transmit Data Buffer (PMBTXBUF)
10.10.3 PMBus Receive Data Register (PMBRXBUF)
10.10.4 PMBus Acknowledge Register (PMBACK)
10.10.5 PMBus Status Register (PMBST)
10.10.6 PMBus Interrupt Mask Register (PMBINTM)
10.10.7 PMBus Control Register 2 (PMBCTRL2)
10.10.8 PMBus Hold Slave Address Register (PMBHSA)
10.10.9 PMBus Control Register 3 (PMBCTRL3)
11 Timer Module Overview
11.1 T24 - 24 Bit Free-Running Timer with Capture and Compare
11.2 T24 Clock Source, Prescaler and Counter
11.3 T24 Capture Block
11.4 T24 Compare Blocks
11.5 T24 Interrupts
11.6 T16PWMx - 16 Bit PWM Timers
11.7 T16PWMx Summary
11.8 T16PWMx Prescaler and Counter
11.9 T16PWMx Compare Blocks
11.10 T16 Shadow Bit
11.11 T16 Interrupts
11.12 Using the T16 for a Timer Interrupt
11.13 Using the T16 for PWM Generation
11.14 WD - Watchdog
11.15 Watchdog Prescale and Counter
11.16 Watchdog Compare Blocks
11.17 Watchdog Protect Bit
11.18 Watchdog Timer Example
11.19 Warnings for Watchdog Status Register
11.20 System Fault Recovery Basics
11.21 Timer Module Register Reference
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Copyright © 2016, Texas Instruments Incorporated
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SNIU028A - February 2016 - Revised April 2016
www.ti.com
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