Texas Instruments UCD3138 Technical Reference Manual page 418

Timer Module Register Reference
Table 11-13. PWMx Compare Control Register (T16PWMxCMPCTRL) Register Field
Bit Field
3 CMP1_INT_ENA
2 CMP1_INT_FLAG
1 CMP0_INT_ENA
0 CMP0_INT_FLAG
418
Timer Module Overview
Descriptions (continued)
Type Reset
R/W 0
Compare 1 Interrupt Enable
0 = Disables Compare 1 Interrupt (Default)
1 = Enables Compare 1 Interrupt
R/W 0
Flag which indicates a valid output compare 1 event. This bit is cleared by writing '1'
to this bit or by rewriting T16PWMxCMP1DAT. If a clear and a compare event occurs
at the same time, the flag will remain high (set has priority versus write clear).
0 = No compare event since last clear
1 = Compare event since last clear
R/W 0
Compare 0 Interrupt Enable
0 = Disables Compare 0 Interrupt (Default)
1 = Enables Compare 0 Interrupt
R/W 0
Flag which indicates a valid output compare 1 event. This bit is cleared by writing '1'
to this bit or by rewriting T16PWMxCMP0DAT. If a clear and a compare event occurs
at the same time, the flag will remain high (set has priority versus write clear).
0 = No compare event since last clear
1 = Compare event since last clear
Copyright © 2016, Texas Instruments Incorporated
Description
SNIU028A – February 2016 – Revised April 2016
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