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2.16.10 1.16.10 Event Update Select
The EVENT_UP_SEL enables 4 different modes of DPWM Event Updating. The DPWM needs a period of
72 nanoseconds (nominal) to update its timing for the next period. During this period, it takes the latest
Filter outputs and any firmware changes to register values and recalculates the timing of the DPWM
signals. The time selected for update should NOT have any DPWM edges moving in or out of the
window.
If DPWM edges move in or out of the Event Update Window, those transitions
may be missed, leading to DPWM pulses longer or shorter than expected.
The modes are:
•
0 - As soon as Filter calculation is done
•
1 - At end of period (starts at end of period, and extends 72ns into start of new period)
•
2 - At time set by sample trigger 2
•
3 - At both End of Period and at time set by sample trigger 2
Note that all modes except for mode 1 make the Event Update timing dependent on the position of the
sample trigger. For most topologies, mode 1 is used, and dead times or minimum pulse widths are used to
keep moving edges out of the first 72nsec of the DPWM period. Please refer to the reference firmware
code provided with UCD3138 EVMs for specific guidance regarding each topology.
2.16.11 Check Override
The CHECK_OVERRIDE bit, when set, overrides the internal DPWM checking. The DPWM checking will
prevent invalid placement of Event settings/period settings or invalid configurations.
Setting this bit may be necessary for some topologies.
2.16.12 Global Period Enable
The GLOBAL_PERIOD_EN bit, if set, enables the use of the Global Period register to provide the period
for this DPWM. It is intended for use with systems which use multiple DPWMs and have need for
frequency dithering. This makes it possible to change the frequency of multiple DPWMs at one location.
For more information, see 5.8 PWM Global Period Register (PWMGLBPRD).
2.16.13 Using DPWM Pins as General Purpose I/O
There are 6 bits in DPWMCTRL1 which can be used to make the DPWM pins into general purpose I/O
pins:
These bits take effect immediately.
•
PWM_A_OE – 0 makes DPWMA into an output if enabled as a GPIO, 1 makes it an input
•
PWM_B_OE – 0 makes DPWMB into an output if enabled as a GPIO, 1 makes it an input
•
GPIO_A_VAL – Value put on DPWMA if it is an output
•
GPIO_B_VAL – Value put on DPWMA if it is an output
GPIO_A_EN – 1 enables DPWMA as a GPIO
GPIO_B_EN – 1 enables DPWMB as a GPIO
In addition, there are 2 bits in the DPWMOVERFLOW register which are also used for GPIO:
•
GPIO_A_IN – reports level on DPWM_A pin if used as input
•
GPIO_B_IN – reports level on DPWM_B pin if used as input
SNIU028A – February 2016 – Revised April 2016
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Copyright © 2016, Texas Instruments Incorporated
DPWM Control Register 1
Digital Pulse Width Modulator (DPWM)
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