Block Write-Block Read Process Call W/O Pec Byte; Block Write-Block Read Process Call With Pec Byte; Alert Response - Texas Instruments UCD3138 Technical Reference Manual

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10.7.9 Block Write-Block Read Process Call
S Device Addr
Byte #(N-1)
Figure 10-41. Block Write-Block Read Process Call w/o PEC Byte
S Device Addr
Byte #(N-1)
Figure 10-42. Block Write-Block Read Process Call with PEC Byte
The Block Read-Block Write Process Call protocol combines the Block Write and Block Read protocols,
removing the stop condition between the two messages. The operation of the Master is similar to a Block
Write operation. Loading the block length into the byte count bits of the Master Control Register provides
the length of the Block Write portion of the message. In addition, the PRC_CALL bit within the Master
Control Register must be enabled. Upon completion of the Block Write part of the message, the PMBus
Interface will automatically issue a Repeated Start condition on the PMBus and start transmission of the
Block Read portion of the message. Operation of the PMBus Interface after the Repeated Start condition
is the same as would be in a simple Block Read Message.

10.7.10 Alert Response

The Alert Response Message is utilized when the Master detects an alert condition from a Slave on the
PMBus. In Master mode, the Alert Response Message is simply a Receive Byte message with PEC
disable and the Slave Address set to 0xC (Alert Response Address). The PMBus Interface detects the
Alert condition on an input and interrupts the firmware indicating the assertion of an alert condition (Slave
desires to communicate with Master). Programming the Master Control Register with the Alert Response
Address, initiates the Alert Response message and provides the device address of the Slave requesting
service. The device address will be found in the Receive Data Register following receipt of the EOM
interrupt.
SNIU028A – February 2016 – Revised April 2016
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Wr A Command
......
A Sr Device Addr Rd
......
Byte #(N-1)
Wr A Command
......
A Sr Device Addr Rd
......
Byte #(N-1)
S Alert Response Addr
Figure 10-43. Alert Response
Copyright © 2016, Texas Instruments Incorporated
A Byte Count = N A
A Byte Count = N A
NA P
A Byte Count = N A
A Byte Count = N A
A PEC NA P
Rd A Device Addr NA
Master Mode Operation Reference
Byte #0 A
Byte #0 A
Byte #0 A
Byte #0 A
P
PMBus Interface/I2C Interface
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