Texas Instruments 27 User Manual
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Texas Instruments 27 User Manual

Texas Instruments 27 User Manual

Texas instruments user's guide power supply ads5525, 27, 45, 46, 47,
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ADS5525/27/45/46/47 EVM User
Guide
User's Guide
November 2006
SLWU028B

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Summary of Contents for Texas Instruments 27

  • Page 1 ADS5525/27/45/46/47 EVM User Guide User's Guide November 2006 SLWU028B...
  • Page 2 SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Overview EVM Basic Functions EVM Quick Start Guide EVM LVDS Output Mode Quick Start (Default) EVM CMOS Output Mode Quick Start Circuit Description Schematic Diagram Circuit Function Expansion Options Custom FPGA Code Expansion Slot Optional USB SPI Interface Physical Description PCB Layout Bill of Materials PCB Schematics...
  • Page 4 ADS5547 SNR Performance vs Decoupling THS4509 + ADS5545 EVM Performance Eye Diagram of Data on Header J4. Top Layer Layer 2, Ground Plane Layer 3, Power Plane #1 Layer 4, Power Plane #2 Layer 5, Ground Plane Layer 6, Bottom Layer DIP Switch SW1 EVM Power Options Output Connector J4...

  • Page 5: Overview

    Overview This manual assists users in using the ADS5525/27/45/46/47 evaluation module (EVM) for evaluating the performance of the ADS5525/27/45/46/47 (ADCs). The EVM provides a powerful and robust capability in evaluation of the many features of the ADCs and the performance of the device der many conditions.

  • Page 6: Evm Quick Start Guide

    EVM Quick Start Guide EVM Quick Start Guide The ADC has two basic modes of output operation, ensuring compatibility in a broad range of systems. Follow the steps below to get the EVM operating quickly with the ADC in either DDR LVDS output mode or CMOS output mode.

  • Page 7: Circuit Description

    www.ti.com Circuit Description Schematic Diagram The schematic diagram for the EVM is in Circuit Function The following paragraphs describe the function of individual circuits. See the data sheet for complete device operating characteristics. 3.2.1 Configuration Options The EVM provides a DIP switch, SW1, to control many of the modes of operation when the EVM is configured for parallel-mode operation.

  • Page 8: Ads5547 Snr Performance Vs Decoupling

    Circuit Description BANANA JACK NAME Device AGND AGND Device AVDD Amplifier negative rail Amplifier positive rail Auxiliary power Device DVDD DGND DGND 9.97 19.94 30.13 Figure 1. ADS5547 SNR Performance vs Decoupling 3.2.3 Analog Inputs The EVM can be configured to provide the ADC with either transformer-coupled or differential amplifier inputs from a single-ended source.

  • Page 9: Ths4509 + Ads5545 Evm Performance

    www.ti.com The schematics present various interface options between the amplifier and the ADC. Depending on the input frequencies of interest, further performance optimization can be had by designing a corresponding filter. In its default configuration, R43, R44, and C119 form a first-order, low-pass filter with a cutoff frequency of 70 MHz.

  • Page 10: Output Connector J4

    Circuit Description J4 PIN Table 3. Output Connector J4 ADS5525/27 DESCRIPTION ADS5545/46/47 DESCRIPTION Reserved Reserved Reserved Reserved Data bit 0 (LSB) Data bit 1 Data bit 0 (LSB) Data bit 2 Data bit 1 Data bit 3 Data bit 2...

  • Page 11: Eye Diagram Of Data On Header J4

    www.ti.com Figure 3. Eye Diagram of Data on Header J4. 3.2.6 Test Points For added EVM visibility and control, several test points are provided. available. SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback Circuit Description C001 Table 4 summarizes the test points...

  • Page 12: Test Points

    Circuit Description 3.2.7 LED Operation To give greater visibility into the EVM operations, two LEDs are provided, D3 and D4. On power up, D4 is asserted when a successful FPGA boot up is complete. For correct EVM operation, the LED should be asserted at all times.

  • Page 13: Expansion Options

    www.ti.com Expansion Options The EVM offers several exciting possibilities to expand the capabilities of the EVM. This allows the utmost flexibility when prototyping an ADC circuit under conditions that mimic the end system, without the need to develop a custom prototype board. Custom FPGA Code Using a standard JTAG interface on JP1, users have the ability to load custom logic onto the FPGA, rapidly speeding up digital development time.

  • Page 14: Physical Description

    Physical Description Physical Description This chapter describes the physical characteristics and PCB layout of the EVM. PCB Layout The EVM is constructed on a 6-layer, 0.062-inch thick PCB using FR-4 material. The individual layers are shown in Figure 4 through Figure similar performance can be had with careful layout using a single ground plane.

  • Page 15: Layer 2, Ground Plane

    www.ti.com Physical Description K002 Figure 5. Layer 2, Ground Plane SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback...

  • Page 16: Layer 3, Power Plane #1

    www.ti.com Physical Description K003 Figure 6. Layer 3, Power Plane #1 SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback...

  • Page 17: Layer 4, Power Plane #2

    www.ti.com Physical Description K004 Figure 7. Layer 4, Power Plane #2 SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback...

  • Page 18: Layer 5, Ground Plane

    www.ti.com Physical Description K005 Figure 8. Layer 5, Ground Plane SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback...

  • Page 19: Layer 6, Bottom Layer

    www.ti.com Physical Description K006 Figure 9. Layer 6, Bottom Layer SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback...

  • Page 20: Bill Of Materials

    www.ti.com Physical Description Bill of Materials SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback...

  • Page 21: Bill Of Materials

    www.ti.com VALUE FOOTPRINT 47- F, tantalum, 20%, 10-V 7343 10- F, 10-V, 20% 3528 10- F, 10-V, 20% 3216 100- F, 6.3-V, 10% 6032 0.1- F, 16-V, 10% 2.2- F, 6.3-V, 10% 10- F, 6.3-V, 10% 0.01- F, 16-V, 10% 0.1- F, 16-V, 10% 1.5-nF, 50-V, 10% 10-pF, 50-V, 0.5-pF...
  • Page 22 Physical Description VALUE FOOTPRINT 0- , 1/10-W, 5% 0- , 1/10-W, 5% 4.02- , 1/10-W 1% 20- , 1/16-W, 1% 24.9- , 1/16-W, 1% 4.7- , 1/2-W, 5% 36- , 1/10-W, 1% 49.9- , 1/16-W, 1% 100- , 1/16-W, 0.1% 200- , 1/16-W, 1% 330- , 1/16-W, 5% 499- , 1/16-W, 1%...
  • Page 23 www.ti.com VALUE FOOTPRINT Ferrite bead 1206 Inductor, SMT, 15- H, 2.6-A COIL-CDRH8D43 Inductor, SMT, 5- H, 2.9-A COIL-CDRH6D38 0.0- , 1/8-W, 5% resistor Red test point Test_point2 Black test point Test_point2 40-pin header 20 2 .1 40-pin header smt 20X2_SMT_MMS_ SAMTEC Red banana jacks BANANA_JACK...
  • Page 24 Physical Description VALUE FOOTPRINT ADS5525/27, ADS5545/46/47 48-QFN_MOD Spartan-3E XC3S250E 256-BGA- 1mm_XILINX IC amp, fully-diff, wideband 16-QFN(RGT) XCF16PFSG48 48PIN_BGA_XILINX IC, pwr-mgmt, triple-supply 20-pin-QFN IC, LDO reg, hi-PSRR, 1.8-V 5-SOT(DBV) IC, comparator, R-R, hi-spd 8-TSSOP(DCN) IC, EX-OR gate, 2-in 5-SOT(DBV) 2-pos shunt...

  • Page 25: Pcb Schematics

    www.ti.com PCB Schematics The schematics for the EVM are on the following pages. SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback Physical Description...
  • Page 26 DRVDD .1uF 10uF .1uF .1uF .1uF U1-H6 (Sh 4) U1-H6 U1-H5 3.3V (Sh 4) U1-H5 4.99K (Sh 4) (Sh 4) (Sh 4) (Sh 4) CLKP (Sh 4) CLKM DRVDD (Sh 2) 3.3V (Sh 2) 3.3V C115 C117 C116 .1uF 2.2uF TLV3502 .1uF +IN A...
  • Page 27 SMA_END .1uF 69.8 (Sh 1) .1uF .1uF 49.9 (Note 1) TC4-1W .1uF Note 1. Part not installed +VCC .1uF .1uF 10uF 10uF Vout+ Vin- 0 ohm THS4509 Vin+ Vout- 0 ohm 69.8 -VCC 49.9 .1uF .1uF 10uF 10uF .22uF 24.9 .1uF .1uF 49.9...
  • Page 28 CLK_INM (Note 1) Note 1. Part not installed (Note 1) CLK_INP 49.9 (Note 1) TC4-1W (Note 1) .1uF SJP2 CLKP CLKP (Sh 1) (1-2) .1uF CLKM SJP1 CLKM (Sh 1) (1-2) Title: Engineer: J. VENABLE DOCUMENTCONTROL # Drawn By: Y. DEWONCK FILE: DATE: 12500 TI Boulevard.
  • Page 29 CLKOUT 20 Ohm ADC_D0 ADC_D1 ADC_D2 ADC_D3 ADC_D4 ADC_D5 ADC_D6 ADC_D7 ADC_D8 ADC_D9 ADC_D10 ADC_D11 ADC_D12 ADC_D13 ADC_D14 ADC_D15 20 Ohm 40PIN_IDC 3.3V BUSY (Sh 5) BUSY INIT_B (Sh 5) INIT_B ADC_D7 ADC_D8 ADC_D9 ADC_D10 ADC_D13 ADC_D12 ADC_D11 (Sh 1) ADC_D14 ADC_D15 CCLK...
  • Page 30 2.5V 1.8V XCF16PFSG48 INIT_B VCCINT OE/RESET__ VCCINT CCLK VCCINT CE__ BUSY BUSY 3.3V CLKOUT VCCO VCCO VCCO VCCO VCCJ IO/HDC CF__ CEO__ REV_SEL0 REV_SEL1 (Sh 3) EN_EXT_SEL__ Note 1. Part not installed 3.3V LED_1206 4.75K 2.5V DTC114EET1 INIT_B (Sh 4) 4.75K CCLK (Sh 4)
  • Page 31 .01uF 1.5nF 1.5nF TP11 100uF 2.5V TPS75003 OUT3 1.2V 10uF 3.3V 61.9K CON_3TERM_SCREW 15.4K TP12 1.5nF TP13 TPS73018DBV .1uF Note 1. Part not installed 1.2V CDRH8D43-150 15uH 100uF FET-SI2323DS SS32 .033 .1uF .1uF .033 36.5K 61.9K 10pF 3.3V CDRH6D38-5R0 FET-SI2323DS 100uF MBRM120 1.8V...
  • Page 32 ADC Analog Supply (+3.3V) +3.3VA-PS AVDD .1uF .1uF 47uF 10uF BLACK ADC DIGITAL SUPPLY(3.3V) OUTPUT_BUFFER DRVDD .1uF .1uF 47uF 10uF BLACK Note 1. Part not installed BLACK BLACK (Note 1) (Note 1) (Note 1) FB10 Diff Amp Positive Supply (+5.0V) +VCC .1uF 47uF...
  • Page 33 EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use.
  • Page 34 Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 It is important to operate this EVM within the AVDD voltage range of –0.3 V to 3.8 V and the DVDD voltage range of –0.3 V to 3.8 V.

  • Page 35: Important Notice

    TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

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