Clock Control Register (Clkcntl); Clock Control Register (Clkcntl) Register Field Descriptions; Register Map - Texas Instruments UCD3138 Technical Reference Manual

Central Interrupt Module (CIM)

16.4.7 Register Map

Address Register Name
0xFFFF FF20 IRQIVEC
0xFFFF FF24 FIQIVEC
0xFFFF FF28
0xFFFF FF2C FIRQPR
0xFFFF FF30 INTREQ
0xFFFF FF34 REQMASK
16.5 SYS – System Module Registers Reference
SYS Registers have the following attributes:
• 16-bit wide
• Addresses placed on word boundaries
• Byte, half-word and word writes permitted
• All Registers can be read in any mode of operation.
• Global Control Register is writeable in privilege mode only. All other Registers are writeable in any
mode.

16.5.1 Clock Control Register (CLKCNTL)

Address FFFFFFD0
The clock control Register configures the MCLK divider for low power modes and the clock multiplexer
which drives the Sync pin when configured to output the CLKOUT signal. CLKCNTRL is accessible in user
and privilege mode and supports byte, half-word and word accesses. Any access to this Register takes
two SYSCLK cycles.
9 8
M_DIV_RATIO Reserved
R-00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-4. Clock Control Register (CLKCNTL) Register Field Descriptions
Bit Field
9-8 M_DIV_RATIO
7 Reserved
6-5 CLKSR
4 Reserved
508
Control System Module
Description
IRQ Index Offset Vector Register
FIQ Index Offset Vector Register
RESERVED
FIQ/IRQ Program Control Register
Pending Interrupt Read Location
Interrupt Mask Register
Figure 16-4. Clock Control Register (CLKCNTL)
7 6 5
CLKSR
R-0 R/W-00
Type Reset
R 00
MCLK (Processor Clock) Divide Ratio
00 = MCLK frequency equals High Frequency Oscillator divided by 8 (Default)
01 = MCLK frequency equals High Frequency Oscillator divided by 16
10 = MCLK frequency equals High Frequency Oscillator divided by 32
11 = MCLK frequency equals High Frequency Oscillator divided by 64
R 0
R/W 00
These bits control the source/function of CLKOUT
00 = Driven by value in CLKDOUT (Bit 3) (Default)
01 = Driven by the interface clock (ICLK)
10 = Driven by the CPU clock (MCLK)
11 = Driven by the system clock (SYSCLK)
R 0
Copyright © 2016, Texas Instruments Incorporated
Table 16-3.
Bits
8
8
32
32
32
4 3
Reserved CLKDOUT
R-0 R/W-0
Description
SNIU028A – February 2016 – Revised April 2016
www.ti.com
Read Write Reset
Yes No 8'h0
Yes No 8'h0
Yes Yes 32'h0
Yes Yes 32'h0
Yes Yes 32'h0
2 0
Reserved
R-000
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