Dpwm Period Register (Dpwmprd) All Other 4 Ns Registers With Standard Alignment Are The Same; Dpwm Sample Trigger 1 Register (Dpwmsamptrig1); Dpwm Event 2 Register (Dpwmev2) Event 3 And 4 Are The Same, Cycle Adjust Registers Only Go To Bit - Texas Instruments UCD3138 Technical Reference Manual

Time Resolution of Various DPWM Registers
Table 2-1. DPWM Register Time Resolutions in UCD3138 (continued)
Register
Resonant Duty
On the UCD3138, all these registers are aligned so that their bit fields match the scaling, except for the
Resonant Duty and Adaptive Sample register. All the registers are unsigned, except for the 2 adjust
registers, Resonant Duty and Adaptive Sample register, which are signed to permit positive or negative
adjustment.
The Resonant Duty register is used in the UCD3138 LLC reference firmware (implemented in
UCD3138LLCEVM-028 EVM) as a 14 bit unsigned register. It can also be used as a 16 bit signed register.
See Section 2.21.
This means that the Phase Trigger, Period, and Event1 registers ignore the 4 least significant bits, as
shown below:
All other 4 ns registers with standard alignment are the same.
Bit Number
Bit Name
Access
Default
The Sample Trigger registers ignore the 6 least significant bits, as shown here:
Table 2-3. DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)
Bit Number
Bit Name
Access
Default
Only the Event 2, 3, and 4 registers use all 18 bits of the field, as shown below.
This means that in all these registers, each bit has the same weight in terms of time. This makes
configuration simpler, since all register loads can use the same time base.
To use this feature, use the .all extension on the register structure. The bit fields do not include the
ignored bits.
All of these C statements put 10 microseconds into the respective registers. Note that the "Low" resolution
clock is at 4 nanoseconds, and "High" resolution is at 250 picoseconds So the corresponding numbers for
the registers are 2,500 and 40,000 respectively.
Dpwm0Regs.DPWMPRD.all = 40000; //includes 4 unused least significant bits
Dpwm0Regs.DPWMPRD.bit.PRD = 2500; //only puts in PRD bit field = 40000/16
Dpwm0Regs.DPWMEV1.all = 40000; //includes 4 unused bits
Dpwm0Regs.DPWMEV1.bit.EVENT1 = 2500; //EV1 is the only low resolution event register
Dpwm0Regs.DPWMEV2.all = 40000; //EV2 is high resolution, so
52
Digital Pulse Width Modulator (DPWM)
4 ns.
Table 2-2. DPWM Period Register (DPWMPRD)
00_0011_0100_0001
SAMPLE_TRIGGER
0000_0010_0000
Table 2-4. DPWM Event 2 Register (DPWMEV2)
Event 3 and 4 are the same, Cycle Adjust registers
only go to bit 15
Bit Number
Bit Name
Access
Default
Copyright © 2016, Texas Instruments Incorporated
Resolution Number of Bits
16 (signed) or
14 (unsigned)
17:4
PRD
R/W
17:6
R/W
17:0
EVENT2
R/W
00_0000_0001_0110_0011
SNIU028A – February 2016 – Revised April 2016
www.ti.com
Bit Alignment
4 ns LSbit
3:0
RESERVED
-
0000
5:0
RESERVED
-
00_0000
Submit Documentation Feedback