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Ramp Module
3.3.8 Sync FET Soft On/Off using Ramp Module
The Sync FET soft on/off can be used to control the on-time of DPWMB in normal mode. DPWMB can be
ramped up and down. It can be used in conjunction with digital or analog IDE (Ideal Diode Emulation).
These two modules control the width of DPWMB as shown below:
Figure 3-8. Ideal Diode Emulation (IDE) Module in UCD3138
The Sync FET Ramp is similar to the DAC Ramp, and uses the same hardware, but it needs a starting
point, which is provided by the SYNC_FET_RAMP_START bits in the RAMPCTRL register. These bits are
scaled at 1 high speed clock cycle per bit (nominally 4 nanoseconds). The
RAMPDACEND.RAMP_DAC_VALUE register is used for the end of the Sync FET Ramp as well, with the
same scaling as the start register.
The fractional position of the step size register is the same, which means that bit 10 in the step size
register represents a 4 nanosecond step.
All the same start criteria can be used for the Sync FET Ramp. The difference is that the SYNC_FET_EN
bit is set in the RAMPCTRL register, instead of the RAMP_EN bit.
The Sync FET ramp only works in normal mode. It cannot be used with Cycle By Cycle (CBC) current
limit, or with any form of Peak Current mode. For Sync FET Ramp to work correctly, the rising edge of
DPWMB must be controlled by the filter. The falling edge of DPWMB is calculated by the DPWM logic
during the update window. When SyncFET ramp is enabled, make sure to place EVT4 at the end of
period or zero.
Any DPWM can be driven by any ramp generator, see the DPWM documentation for ramp selection as
well.
The Ramp Module is also used in the DAC Ramp and in Prebias, so only one of these functions can be
done by each Ramp Module at a time.
Note: Even if the Ramp Module is being used for Sync FET soft on/off, it is not possible to write to the
EADCDAC for that front end while the Ramp Module is being used.
122
Front End
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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