Front End Control Muxes (Fectrl0Mux, Fectrl1Mux, Fectrl2Mux); Sample Trigger Control (Samptrigctrl); External Dac Control (Extdacctrl) - Texas Instruments UCD3138 Technical Reference Manual

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5.1

Front End Control Muxes (FECTRL0MUX, FECTRL1MUX, FECTRL2MUX)

These registers select what DPWM signals are used to trigger DAC control functions in the Front end,
Ramp and Dither. The selected signals are also used when the Ramp Module is used for Sync FET
ramps. Two signals can be used:
1. Rising edges of DPWMA and DPWMB from all DPWM modules
2. Frame sync from all DPWM Modules
Frame sync occurs at the beginning of the DPWM period. It always occurs whenever the DPWM is
running. DPWMA and DPWMB are dependent on the actual rising edges of DPWMA and DPWMB. If no
DPWM pulse is occurring, then the trigger will not take place. DPWMA_F and DPWMB_F are used. These
are the signals coming out of the Fault Block, as shown in
modules which prevents DPWMA and DPWMB from going high will prevent triggering of the Front End by
these signals. Anything further down in the signal chain, such as the Intra Mux or the Edge Generator will
have no effect at all.
This trigger should not be confused with the sample trigger, which triggers the EADC conversion. Ideally
the DAC control function should be triggered just after the end of the EADC conversion to allow maximum
DAC settling time. For DAC settling time, please refer to the UCD3138 device datasheet.
The FECTRLxMUX registers also permit using the Nonlinear Select registers in the Filter to set the step
points for Automatic Gain Shifting in the Front End.
For exact FECTRLxMUX bit assignments, see:
(FECTRL0MUX).
5.2

Sample Trigger Control (SAMPTRIGCTRL)

The SAMPTRIGCTRL register has a bit for each combination of Front End and DPWM module. As a
default, none of these bits are set, so no sample triggers are enabled. Any DPWM can trigger any Front
End. Multiple triggers can be used for any Front End, and multiple Front Ends can use the same trigger.
The DPWMs can generate two triggers (A and B). They can generate multiple triggers – oversampling. All
of this is automatically transmitted to the Front End if the bit in SAMPTRIGCTRL is set. See
Section 5.14.4, Sample Trigger Control Register (SAMPTRIGCTRL), for the register details.
5.3

External DAC Control (EXTDACCTRL)

The EXTDACCTRL register permits control of the EADCDAC in each Front End from different sources. If
the EXT_DACx_EN bit is 0, the Front End controls its own DAC. If EXT_DACx_EN is 1, other sources will
have control:
1. Other EADCDACs – this can be used to slave two Front Ends together.
2. Output of Constant Power Module – this is used for constant power control
3. Filter x Output – this is used to put loops in series, for example, a voltage loop can control a current
loop by using the voltage loop output to control the EADCDAC for the current loop.
See Section 5.14.5, External DAC Control Register (EXTDACCTRL), for bitfield details.
SNIU028A – February 2016 – Revised April 2016
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Front End Control Muxes (FECTRL0MUX, FECTRL1MUX, FECTRL2MUX)
Section 5.14.1, Front End Control 0 Mux Register
Copyright © 2016, Texas Instruments Incorporated
Figure 2-1. Anything in the Timing or Fault
187
Loop Mux