Light Load Control Register (Llctrl); Light Load Control Register (Llctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

Loop Mux Registers Reference

5.14.24 Light Load Control Register (LLCTRL)

Address 0002005C
25
7 6
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-25. Light Load Control Register (LLCTRL) Register Field Descriptions
Bit Field
25-8 DPWM_ON_TIME
7-4 Reserved
3 CYCLE_CNT_EN
2-1 LL_FILTER_SEL
0 LL_EN
220
Loop Mux
Figure 5-25. Light Load Control Register (LLCTRL)
DPWM_ON_TIME
R/W-00 0000 0000 0000 0000
5 4
R-0000
Type Reset
R/W 00 0000
DPWM pulse width used for EADC-based light load mode operation, when selected
0000
Filter data exceeds TURN_ON_THRESH value
0000
0000
R 0000
R/W 0
Enables Switching Cycle Counter for enabling constant pulse widths when
configured in Light Load operation
0 = Switching Cycle Counter disabled (Default)
1 = Switching Cycle Counter enabled
R/W 00
Configures source of filter data for Light Load comparisons
0 = Filter 0 data selected (Default)
1 = Filter 1 data selected 2 = Filter 2 data selected
R/W 0
EADC-based Light Load Mode Enable
0 = Light Load Mode disabled (Default)
1 = Light Load Mode enabled
Copyright © 2016, Texas Instruments Incorporated
3 2
CYCLE_CNT LL_FILTER_SEL
_EN
R/W-0 R/W-00
Description
SNIU028A – February 2016 – Revised April 2016
www.ti.com
8
1 0
LL_EN
R/W-0
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