2.16.2 Sync Fet Ramp Enable; 2.16.3 Burst Mode Enable; 2.16.4 Current/Flux Balancing Duty Adjust; 2.16.5 1.16.5 Sync Out Divisor Selection - Texas Instruments UCD3138 Technical Reference Manual

DPWM Control Register 1

2.16.2 Sync FET Ramp Enable

The SYNC_FET_EN bit enables the Sync FET Ramp logic to take control of DPWM B. For more on the
Ramp logic, see Section
DPWMMUX register in the Loop Mux. The following code enables Sync FET Ramp for DPWM0, and sets
up Front End 0's Ramp Engine to provide the ramp source.
LoopMuxRegs.DPWMMUX.bit.DPWM0_SYNC_FET_SEL = 0;
//use ramp engine on Front End 03
Dpwm0Regs.DPWMCTRL1.bit.SYNC_FET_EN = 1; //enable sync FET ramp
The Sync FET Ramp logic ramps the pulse width of DPWMB up from a starting point to a width controlled
by Normal mode, or by the IDE function, if enabled. It only works in Normal mode.

2.16.3 Burst Mode Enable

Setting the BURST_EN bit enables burst (light load) mode for this DPWM. For more information on Light
load mode, see the light load section.

2.16.4 Current/Flux Balancing Duty Adjust

Setting the CLA_DUTY_ADJ_EN bit enables the Current Balancing logic to modify the input to the DPWM
so that current controlled by this DPWM can be balanced with the current controlled by another DPWM in
the same UCD3138. For more information,

2.16.5 1.16.5 Sync Out Divisor Selection

The SYNC_OUT_DIV_SEL bit field selects a divisor generating the sync out pulse on the external sync
out pin. It is only effective on the sync out, not on internal chip sync signals sent to other DPWMs.
The divisor has 4 bits, and a range from 1 to 16 for the divisor. The divisor = SYNC_OUT_DIV_SEL + 1.
So 0 in the bit field would give a divisor of 1, 1 gives a divisor of 2, and so on.

2.16.6 FIlter Scale

The CLA_SCALE bits control shifting of the Filter Duty output before it is used by the DPWM. Shifts
available range from a 3 bit right shift to a 3 bit left shift. The Filter Period is not scaled by these bits.
The default value, 0, causes no shift. For the shift table, see
This can be used in complex topologies where the same filter output is needed for different circuits at
different frequencies. It can also be used to change the overall gain of the Filter.

2.16.7 External Sync Enable

Setting the EXT_SYNC_EN bit causes the DPWM to use the Sync In pin as a source for Sync.

2.16.8 Cycle By Cycle B Side Active Enable

Setting the EXT_SYNC_EN bit causes the DPWM to use the Sync In pin as a source for Sync.

2.16.9 Auto Mode Switching Enable

The AUTO_MODE_SEL bit, when set, enables auto mode switching.
60
Digital Pulse Width Modulator (DPWM)
3.3.8. The Front End which provides the Ramp data is selected in the
see the Current Balancing section.
Copyright © 2016, Texas Instruments Incorporated
Section 2.31.2.
SNIU028A – February 2016 – Revised April 2016
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