Pre-Bias Control Register 0 (Prebiasctrl0); Pre-Bias Control Register 0 (Prebiasctrl0) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

Front End Control Registers

3.7.11 Pre-Bias Control Register 0 (PREBIASCTRL0)

Address 0x0008_0028 – Front End Control 2 Pre-Bias Control Register 0
Address 0x000B_0028 – Front End Control 1 Pre-Bias Control Register 0
Address 0x000E_0028 – Front End Control 0 Pre-Bias Control Register 0
17 16
PRE_BIAS PRE_BIAS_EN
_POL
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-13. Pre-Bias Control Register 0 (PREBIASCTRL0) Register Field Descriptions
Bit Field
17 PRE_BIAS_POL
16 PRE_BIAS_EN
15-8 PRE_BIAS
_RANGE
7-0 PRE_BIAS_LIMIT
136
Front End
Figure 3-19. Pre-Bias Control Register 0 (PREBIASCTRL0)
15
PRE_BIAS_RANGE
R/W-1111 1111
Type Reset
R/W 0
Configures polarity of received error voltage
0 = Error equals Vref-Vin (Default)
1 = Error equals Vin-Vref
R/W 0
Enable Pre-Biasing of Error ADC (Ramp should be disabled during pre-biasing, bit 0
of Ramp Control Register)
0 = Pre-Biasing has not been initiated (Default)
1 = Pre-Biasing by hardware has been enabled
R/W 1111
Sets the acceptable range around the zero error point. If Error ADC value stays in
1111
range for number of samples specified by PRE_BIAS_LIMIT (Bits 7:0),
PREBIAS_STATUS (Bit 0 of Ramp Status Register) is enabled. Range will be +/-
PRE_BIAS_RANGE around zero error point.
R/W 0000
Sets the acceptable number of samples in which the Error ADC value stays in range
0000
before asserting PREBIAS_STATUS (Bit 0 of Ramp Status Register). Counter limit
ranges from 0 to 255. If PREBIAS_STATUS is set, it will take PRE_BIAS_LIMIT
samples outside of acceptable range before clearing PREBIAS_STATUS.
Copyright © 2016, Texas Instruments Incorporated
8 7
PRE_BIAS_LIMIT
R/W-0000 0000
Description
SNIU028A – February 2016 – Revised April 2016
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