Adc Control Register (Adcctrl); Adc Control Register (Adcctrl) Register Field Descriptions; Adc Registers - Texas Instruments UCD3138 Technical Reference Manual

ADC Registers

// Means: Enable Digital comparator 3 interrupt when exceeding upper limit at Local level
AdcRegs.ADCCOMPLIM[5].bit.LOWER_LIMIT = 0x0FA;
// Sets the lower limit to be compared to the sixth result register
//( Note: bit does not necessarily mean one bit, but a bits field of any length
CimRegs.REQMASK.bit. REQMASK_DIGI_COMP =1;
// Means: Enable Digital comparator interrupt at CPU(CIM) level.
8.18 ADC Registers

8.18.1 ADC Control Register (ADCCTRL)

Address 00040000
31
23 22
EXT_TRIG_GP EXT_TRIG_GP
IO_VAL IO_DIR
R/W-0 R/W-0
15
SAMPLING_SEL
R/W-000
7
MAX_CONV
R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-5. ADC Control Register (ADCCTRL) Register Field Descriptions
Bit Field
31-24 EXT_TRIG_DLY
23 EXT_TRIG_GPIO_
VAL
22 EXT_TRIG_GPIO_
DIR
21 EXT_TRIG_GPIO_
EN
20 EXT_TRIG_EN
316
ADC12 Overview
Figure 8-19. ADC Control Register (ADCCTRL)
EXT_TRIG_DLY
R/W-0000 0000
21 20
EXT_TRIG_GP EXT_TRIG_EN
IO_EN
R/W-0 R/W-0
13 12
ADC_SEL_REF
R/W-0
4
Type Reset
R/W 0000
8-bit External ADC Trigger Delay configuration, LSB bit resolution equals period of
0000
ADC Clock (High Frequency Oscillator Frequency divided by 4)
R/W 0
Output value of ADC_EXT_TRIG pin when configured in GPIO mode
0 = ADC_EXT_TRIG pin driven low (Default)
1 = ADC_EXT_TRIG pin driven high
R/W 0
Direction of ADC_EXT_TRIG pin when configured in GPIO mode
0 = ADC_EXT_TRIG pin configured as input (Default)
1 = ADC_EXT_TRIG pin configured as output
R/W 0
Configuration of ADC_EXT_TRIG pin
0 = ADC_EXT_TRIG pin configured in functional mode (Default)
1 = ADC_EXT_TRIG pin configured in GPIO mode
R/W 0
External Trigger Enable, conversions are started using the external trigger as
selectable by the EXT_TRIG_SEL bits.
0 = Disable External Trigger capability (Default)
1 = Enable External Trigger capability
Copyright © 2016, Texas Instruments Incorporated
19
EXT_TRIG_SEL
R-0000
11 10
ADC_ROUND
R/W-0
3 2
SINGLE_ SW_START
SWEEP
R/W-0 R/W-0
Description
SNIU028A – February 2016 – Revised April 2016
www.ti.com
24
16
8
BYPASS_EN
R/W-111
1 0
ADC_INT_EN ADC_EN
R/W-0 R/W-0
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