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As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking
intervals are mainly useful for the edges at the beginning and end of the period.
2.9
Sync FET Ramp and IDE Calculation
For many topologies, it is useful to replace diodes with synchronous rectification (SR), a concept also
known as Ideal Diode Emulation (IDE). In continuous conduction mode, the SR FET control is simple,
because it can be turned on for the entire off time of the primary FET, minus a dead time. This is handled
perfectly by Normal mode. The Sync FET Ramp and IDE calculation are only available in Normal mode.
They are not compatible with the Cycle by Cycle Fault module.
However, in discontinuous mode, the SR FET needs to be turned off before the end of the period. The
UCD3138 hardware provides an automatic function to make this easier. In this case, the falling edge of
DPWMB is adjusted, as shown below:
Period Counter
DPWM0 Output A
DPWM0 Output B Trailing edge
Sync FET edge on DPWM B controlled by Ramp logic and/or Integrated Diode equation
The digital hardware implements the equation D
calculates Kd. For example, for a Buck topology, K
FET, D
is duty cycle of SR FET, V
b
measures the slowly changing V
hardware adjusts D
rapid changes in D
When starting up in prebias mode i.e. with a voltage already present on the outputs, it is difficult to
accomplish precise diode emulation (IDE). One solution to this issue is to ramp the voltage up to the
target without synchronous rectification (SR), and then to activate SR after the voltage is regulated. When
activating or de-activating SR, in order to avoid glitches in the regulated voltage, it is best to gradually
increase/decrease the Sync FET on-time. The UCD3138 provides what is termed as Sync FET Soft-
On/Soft-Off (ramp) logic to accomplish this. This is documented in
Front End is used for this function. It will ramp up to either the limits imposed by normal mode, or to the
limits imposed by the IDE logic.
With digital IDE enabled, as the system transitions from discontinuous mode into continuous conduction
Mode (sync FET is on until end of the period) the IDE will stop reducing the Sync FET pulse width. This is
because the reverse conduction through the Sync FET will keep Da and Db the same. It is necessary to
detect DCM (Discontinuous Conduction Mode) current levels in the IDE approach. Once these levels are
detected, the Sync FET should be ramped down, and then ramped back up with IDE enabled.
SNIU028A – February 2016 – Revised April 2016
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Normal Mode with Sync FET IDE and/or Ramp
DPWM0 Start of Period
Period
Da
Stays within dead time limits for Normal Mode
Figure 2-10. SyncFET IDE (Normal Mode)
is input voltage and V
in
and V
, and puts the calculated result into the K
in
out
every switching cycle, maintaining proper IDE even during transients which cause
b
.
a
Copyright © 2016, Texas Instruments Incorporated
DPWM0 Start of Period
Da
Db
= D
* K
. The firmware measures Vin and Vout and
b
a
d
= (V
- V
)/V
, where D
d
in
out
out
is output voltage. The firmware periodically
out
Section
Digital Pulse Width Modulator (DPWM)
Sync FET Ramp and IDE Calculation
Db
is duty cycle of the control
a
register. The DPWM
d
3.3.8. The Ramp module in the
47
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