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DPWM Control Register 1
2.16.14 High Resolution enable/disable
There are 5 bits which all enable/disable High Resolution Mode in some way or another
•
PWM_HR_MULT_OUT_EN – Set only for multi mode
•
HIRES_SCALE (2 bits) – Sets resolution of DPWM high res block
•
ALL_PHASE_CLK_ENA – enables all phases or only needed phases
•
HIRES_DIS – disables high res logic
As a general rule, all can be disabled when high resolution is not possible, and all should be enabled
when high resolution is possible and required.
2.16.15 Asynchronous Protection Disable
The PWM_A_PROT_DIS and PWM_B_PROT_DIS bits disable asynchronous protection on their
respective pins. Please consult to the reference firmware code provided with UCD3138 EVMs for specific
guidance on whether to set these bits or not in the desired topology.
2.16.16 Single Frame Enable
The SFRAME_EN bit enables a single frame to be output from the DPWM. It is useful for putting out a
single pulse on the DPWM, and triggering a single Front End and Filter cycle. It can be used, for example,
when measuring input voltage on an isolated supply. To use Single Frame enable, first initialize the
DPWM module and set the SFRAME_EN bit, and enable the DPWM globally. To actually start the single
frame, set the PWM_EN bit. This will trigger a single frame.
2.17 DPWM Control Register 2
The DPWMCTRL2 register, like the other 2 control registers, has a wide selection of bit fields.
2.17.1 External Synchronization Input Divide Ratio
The SYNC_IN_DIV_RATIO bit field has 4 bits, which are initialized to zero at reset. They set the divide
ratio for the synchronization both from the outside and from another DPWM. The divide ratio is the bit field
value plus 1. So 0 is divide by 1, 1 divide by 2, and so on.
2.17.2 Resonant Deadtime Compensation Enable
Setting the RESON_DEADTIME_COMP_EN bit enables a dead time adjustment to the CLA Duty signal
from the Filter. This compensation, which only has an effect in resonant mode, makes it possible to have
constant, fixed, symmetrical dead time in resonant mode for the full range of frequencies. Generally this is
the best configuration for LLC. If the bit is not set, the CLA Duty Signal is used without adjustment. This
leads to DPWMA putting out 50% Duty + Cycle Adjust A, and DPWMB putting 50% - dead time + Cycle
Adjust B, which cannot be made to yield a symmetrical signal on A and B over the frequency range for
LLC.
62
Digital Pulse Width Modulator (DPWM)
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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