Address Byte Timing; Repeated Start Timing; Pmbus Slave Mode Low Level Timing - Texas Instruments UCD3138 Technical Reference Manual

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10.5 PMBus Slave Mode Low Level Timing

These diagrams give the low level timing for the PMBus logic. They show the timing between events on
the PMBus pins and PMBus register changes.
For each timing parameter, only one case is shown. Note that the same timing parameter may occur in
different places in a PMBus message.
Some of the timing diagrams show a clock stretch. These are optional. If the firmware can respond fast
enough, no clock stretch will be necessary.
PMBUS_CLK
PMBUS_DATA
RPT_START
Note: Stretch is optional, depending on firmware timing.
PMBUS_CLK
PMBUS_DATA
UNIT_BUSY
SLAVE_ADDR_READY
DATA_REQUEST(1)
Write to ACK
DATA_REQUEST(2)
SNIU028A – February 2016 – Revised April 2016
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A
Figure 10-17. Address Byte Timing
S Slave Address
1 2
t
START
Figure 10-18. Repeated Start Timing
Copyright © 2016, Texas Instruments Incorporated
PMBus Slave Mode Low Level Timing
S Slave Address
1
t
RPTSTRT
R/W (Stretch)
7 8
t
SAR
t
DREQ1
PMBus Interface/I2C Interface
2
A
t
ACKWRITE
t
DREQ2
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