Pwmx Compare Control Register (T16Pwmxcmpctrl); Pwmx Compare Control Register (T16Pwmxcmpctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

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11.21.13 PWMx Compare Control Register (T16PWMxCMPCTRL)

Address FFF7FD44 – 16-bit PWM0 Compare Control Register
Address FFF7FD68 – 16-bit PWM1 Compare Control Register
Address FFF7FD7C – 16-bit PWM2 Compare Control Register
Address FFF7FD90 – 16-bit PWM3 Compare Control Register
Note – Bits indicated with a * are only available for 16 bit timers which have an external pin associated
with them. On the UCD3138 and most family members, this is only PWM0 and PWM1. On the
UCD3138128 and UCD3138A64 80 pin devices, all 4 timers have an external pin.
Figure 11-16. PWMx Compare Control Register (T16PWMxCMPCTRL)
12
SHADOW
R/W-0
7 6
PWM_OUT_
ACTION1
R/W-00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-13. PWMx Compare Control Register (T16PWMxCMPCTRL) Register Field Descriptions
Bit Field
12 SHADOW
11 *PWM_IN
10 *PWM_OUT
9 *PWM_OUT_ENA
8 *PWM_OUT_DRV
7-6 PWM_OUT_ACTI
ON1
5-4 PWM_OUT_ACTI
ON0
SNIU028A – February 2016 – Revised April 2016
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11
*PWM_IN
R-0
5 4
PWM_OUT_
ACTION0
R/W-00
Type Reset
R/W 0
Controls the update of the 16-bit output compare Registers.
0 = PWM output compare Registers immediately written (Default)
1 = PWM output compare Registers updated through the buffers
T16PWMxCMPyDAT after a match occurs in the corresponding Register
T16PWMxCMPyDAT.
R 0
Input value of PWM pin when configured in PWM mode
0 = Logic level low detected on PWM pin
1 = Logic level high detected on PWM pin
R/W 0
Data to be written into the output latch when PWM_OUT_DRV is high.
0 = Output latch is cleared when PWM_OUT_DRV=1 (Default)
1 = Output latch is set when PWM_OUT_DRV=1
R/W 0
FAN-PWM pin configuration
0 = FAN-PWM configured as an input pin (Default)
1 = FAN-PWM configured as an output pin
R/W 0
Causes the value of the bit PWM_OUT to be written into the output latch. So it is
possible to preload the output latch or to use the pin as GPIO. The compare action
has priority before the preload function. This bit is always read as '0'.
0 = Output latch not affected by the value of PWM_OUT (Default)
1 = Value of OUT written into the output latch
R/W 00
These 2 bits select the output action when a compare equal is detected on
T16CMP1DAT
00 = No action (Default)
01 = Set pin
10 = Clear pin
11 = Toggle pin
R/W 00
Selects the output action when a compare equal is detected on T16CMP0DAT.
00 = No action (Default)
01 = Set pin
10 = Clear pin
11 = Toggle pin
Copyright © 2016, Texas Instruments Incorporated
10
*PWM_OUT *PWM_OUT_ENA
R/W-0
3
CMP1_ CMP1_
INT_ INT_
ENA FLAG
R/W-0 R/W-0
Description
Timer Module Register Reference
9 8
PWM_OUT_DRV
R/W-0 R/W-0
2 1
CMP0_
INT_
ENA
R/W-0
Timer Module Overview
0
CMP0_
INT_
FLAG
R/W-0
417