Erasing Program Flash - Texas Instruments UCD3138 Technical Reference Manual

Address Decoder (DEC)

16.1.13 Erasing Program Flash

Erasing Program Flash is exactly the same as the procedure for Data Flash, above, except that Program
Flash is divided into 32 pages of 1024 bytes each. Of course a different register is used, the
PFLASHCTRL register.
The other issue with Erasing Program Flash is that this is the normal location for programs to run, and it is
not possible to execute from Program Flash while erasing it or writing to it. So a suitable program must be
placed in either Data Flash or RAM, and executed while the functions are being performed.
16.1.14 Writing to Program Flash
The process for writing to Program Flash is exactly the same as the process for writing to Data Flash –
write the key, write to the actual address, and then monitor the BUSY bit. Like Data flash, Program flash
should be written to 4 bytes at a time. Program flash can be written to twice between erases. This is used
in the clear checksum function, where first the checksum is written, and then all zeroes are written to the
checksum to clear it. Writing to the flash more than twice between erases is not guaranteed to work and
hence not recommended.
16.2 Memory Management Controller (MMC)
The MMC manages the interface to the peripherals by controlling the interface bus for extending the read
and write accesses to each peripheral. The unit generates eight peripheral select lines with 1KB of
address space decoding. The interface can be configured with an interface clock from divide by 2 thru 16.
For divide by 2, each peripheral requires two clock accesses.
16.3 System Management (SYS)
The SYS unit contains the software access protection by configuring user privilege levels to memory or
peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal
address or access conditions. Also available is clock control setup for system operation.
16.4 Central Interrupt Module (CIM)
The Central Interrupt Module accepts 32 interrupt requests and provides configurable mapping in order to
meet the firmware timing requirements. The ARM itself only supports two levels of interrupts, FIQ and
IRQ. With FIQ being the higher interrupt to IRQ. The CIM provides hardware expansion of interrupts by
use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index value
indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt
vector address from the interrupt vector table. Interrupt channel 31 has the highest precedence and
interrupt channel 0 has the lowest precedence. The CIM is level sensitive to the interrupt requests and
each peripheral will need to keep the request high until the ARM responds to it. To remove the interrupt
request, the firmware should clear the request as the first action in the interrupt service routine. The
request channels are maskable to selectively disable individual channels.
502
Control System Module
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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