Texas Instruments UCD3138 Technical Reference Manual page 4

2.31.21 DPWM Blanking B Begin Register (DPWMBLKBBEG)
2.31.22 DPWM Blanking B End Register (DPWMBLKBEND)
2.31.23 DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI)
2.31.24 DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO)
2.31.25 DPWM Adaptive Sample Register (DPWMADAPTIVE)
2.31.26 DPWM Fault Status (DPWMFLTSTAT)
2.31.27 DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH)
2.31.28 DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH)
2.31.29 DPWM Auto Switch Low Upper Thresh Register (DPWMAUTOSWLOUPTHRESH)
2.31.30 DPWM Auto Switch Low Lower Thresh Register (DPWMAUTOSWLOLOWTHRESH)
2.31.31 DPWM Auto Config Max Register (DPWMAUTOMAX)
2.31.32 DPWM Auto Config Mid Register (DPWMAUTOMID)
2.31.33 DPWM Edge PWM Generation Control Register (DPWMEDGEGEN)
2.31.34 DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD)
2.31.35 DPWM BIST Status Register (DPWMBISTSTAT)
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3 Front End
3.1 Error ADC and Front End Gain
3.1.1 Front End Gain
3.1.2 EADC Error Output
3.1.3 EADC Triggering, EADC Output to Filter
3.1.4 EADC Timing
3.1.5 EADC Averaging
3.1.6 Enabling EADC and Front End
3.2 Front End DAC
3.3 Ramp Module
3.3.1 DAC Ramp Overview
3.3.2 DAC Ramp Start and End Points
3.3.3 DAC Ramp Steps
3.3.4 DAC Ramp Start, Interrupts, Start Delay
3.3.5 RAMPSTAT Register
3.3.6 DAC RAMP when EADC is Saturated
3.3.7 Using Ramp Module for Peak Current Mode
3.3.8 Sync FET Soft On/Off using Ramp Module
3.4 Successive Approximation Mode
3.4.1 SAR Control Parameters
3.4.2 SAR Algorithm Overview
3.4.3 Non-Continuous SAR Mode
3.4.4 Continuous SAR Mode
3.5 Absolute Value Without SAR
3.6 EADC Modes
3.7 Front End Control Registers
3.7.1 Ramp Control Register (RAMPCTRL)
3.7.2 Ramp Status Register (RAMPSTAT)
3.7.3 Ramp Cycle Register (RAMPCYCLE)
3.7.4 EADC DAC Value Register (EADCDAC)
3.7.5 Ramp DAC Ending Value Register (RAMPDACEND)
3.7.6 DAC Step Register (DACSTEP)
3.7.7 DAC Saturation Step Register (DACSATSTEP)
3.7.8 EADC Trim Register (EADCTRIM) - (For Factory Test Use Only)
3.7.9 EADC Control Register (EADCCTRL)
3.7.10 Analog Control Register (ACTRL) (For Test Use Only)
3.7.11 Pre-Bias Control Register 0 (PREBIASCTRL0)
3.7.12 Pre-Bias Control Register 1 (PREBIASCTRL1)
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Copyright © 2016, Texas Instruments Incorporated
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SNIU028A - February 2016 - Revised April 2016
www.ti.com
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