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UCD3138
User Manuals: Texas Instruments UCD3138 Controller
Manuals and User Guides for Texas Instruments UCD3138 Controller. We have
3
Texas Instruments UCD3138 Controller manuals available for free PDF download: Technical Reference Manual, User Manual
Texas Instruments UCD3138 Technical Reference Manual (532 pages)
Digital Power Supply Controller
Brand:
Texas Instruments
| Category:
Power Supply
| Size: 4 MB
Table of Contents
Ucd3138 Digital Power Supply Controller Technical Reference Manual
2
Table of Contents
2
8
1 Introduction
30
Scope of this Document
30
A Guide to Other Documentation for All Members of UCD3138 Family of Products
30
2 Digital Pulse Width Modulator (DPWM)
33
DPWM Block Diagram
35
Block Diagram of a DPWM Module
35
Block Diagram of Timing Module in the DPWM Module
36
Introduction to DPWM (DPWM Multi-Mode, Open Loop)
37
DPWM Mode - Multi-Mode, Open Loop
38
DPWM Normal Mode
39
DPWM - Normal Mode
39
DPWM Phase Shift Mode
41
DPWM - Phase Shift Mode
41
DPWM Multiple Output Mode (Multi Mode)
42
DPWM - Multiple Output Mode (Multi Mode)
42
DPWM Resonant Mode
43
DPWM - Resonant Mode
44
Triangular Mode
45
DPWM - Triangular Mode
45
DPWM Leading Edge Mode
46
DPWM - Leading Edge Mode
46
Sync FET Ramp and IDE Calculation
47
Syncfet IDE (Normal Mode)
47
2.10 Automatic Mode Switching
48
2.10.1 Resonant LLC Example
48
2.10.2 Mechanism for Automatic Mode Switching
48
Resonant LLC Implementation in UCD3138 with Automatic Mode Switching
48
Mechanism for Automatic Mode Switching in UCD3138
49
2.11 DPWMC, Edge Generation, Intramax
50
UCD3138 Edge-Gen & Intra-Mux
50
2.12 Time Resolution of Various DPWM Registers
51
DPWM Register Time Resolutions in UCD3138
51
DPWM Period Register (DPWMPRD) All Other 4 Ns Registers with Standard Alignment Are the same
52
DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)
52
DPWM Event 2 Register (DPWMEV2) Event 3 and 4 Are the Same, Cycle Adjust Registers Only Go to Bit
52
2.13 PWM Counter and Clocks
53
2.14 DPWM Registers - Overview
53
2.15.1 DPWM Auto Config MID and Max Registers
53
2.15.2 Intra Mux
53
DPWM Control Register 0 (DPWMCTRL0)
53
2.15.3 Cycle by Cycle Current Limit Enable
54
Truth Table
55
2.15.4 Multi Mode On/Off
56
2.15.5 Minimum Duty Mode
56
Minimum Duty Mode
57
2.15.10 DPWM a and B Fault Priority
58
2.15.6 Master Sync Control Select
58
2.15.7 Master Sync Slave Enable
58
2.15.8 D Enable
58
2.15.9 Resonant Mode Fixed Duty Enable
58
2.15.11 Blank Enable
59
2.15.12 DPWM Mode
59
2.15.13 DPWM Invert
59
2.15.15 DPWM Enable
59
2.16.1 Period Counter Preset Enable
59
DPWM Control Register 1
59
Filter Enable (CLA_EN)
59
2.16.2 Sync FET Ramp Enable
60
2.16.3 Burst Mode Enable
60
2.16.4 Current/Flux Balancing Duty Adjust
60
2.16.5 1.16.5 Sync out Divisor Selection
60
2.16.6 Filter Scale
60
2.16.7 External Sync Enable
60
2.16.8 Cycle by Cycle B Side Active Enable
60
2.16.9 Auto Mode Switching Enable
60
2.16.10 1.16.10 Event Update Select
61
2.16.11 Check Override
61
2.16.12 Global Period Enable
61
2.16.13 Using DPWM Pins as General Purpose I/O
61
2.16.14 High Resolution Enable/Disable
62
2.16.15 Asynchronous Protection Disable
62
2.16.16 Single Frame Enable
62
2.17.1 External Synchronization Input Divide Ratio
62
2.17.2 Resonant Deadtime Compensation Enable
62
DPWM Control Register 2
62
2.17.3 Filter Duty Select
63
2.17.4 Ideal Diode Emulation (IDE) Enable for PWMB
63
2.17.5 Sample Trigger 1 Oversampling
63
2.17.6 Sample Trigger 1 Mode
63
2.17.7 Sample Trigger Enable Bits
64
2.18 Period and Event Registers
64
2.19 Phase Trigger Registers
64
2.20 Cycle Adjust Registers
64
2.21 Resonant Duty Register
64
2.22 DPWM Fault Control Register
64
2.23 DPWM Overflow Register
64
2.24 DPWM Interrupt Register
65
2.24.1 DPWM Period Interrupt Bits
65
2.24.2 Mode Switching Interrupt Bits
65
2.24.3 INT Bit
65
2.25 DPWM Counter Preset Register
65
2.26 Blanking Registers
65
2.27 DPWM Adaptive Sample Register
66
2.28 DPWM Fault Status Register
66
2.29 DPWM Auto Switch Registers
66
2.30 DPWM Edge PWM Generation Register
66
2.31 DPWM 0-3 Registers Reference
66
DPWM Control Register 0 (DPWMCTRL0)
66
DPWM Control Register 0 (DPWMCTRL0)
67
DPWM Control Register 0 (DPWMCTRL0) Register Field Descriptions
67
DPWM Control Register 1 (DPWMCTRL1)
70
DPWM Control Register 1 (DPWMCTRL1) Register Field Descriptions
71
DPWM Control Register 1 (DPWMCTRL1)
72
DPWM Control Register 2 (DPWMCTRL2)
73
DPWM Control Register 2 (DPWMCTRL2)
74
DPWM Control Register 2 (DPWMCTRL2) Register Field Descriptions
74
DPWM Period Register (DPWMPRD)
75
DPWM Period Register (DPWMPRD) Register Field Descriptions
75
DPWM Event 1 Register (DPWMEV1)
76
DPWM Event 1 Register (DPWMEV1) Register Field Descriptions
76
DPWM Event 2 Register (DPWMEV2)
77
DPWM Event 2 Register (DPWMEV2) Register Field Descriptions
77
DPWM Event 3 Register (DPWMEV3)
78
DPWM Event 3 Register (DPWMEV3) Register Field Descriptions
78
DPWM Event 4 Register (DPWMEV4)
79
DPWM Event 4 Register (DPWMEV4) Register Field Descriptions
79
DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)
80
DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1) Register Field Descriptions
80
DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2)
81
DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2) Register Field Descriptions
81
DPWM Phase Trigger Register (DPWMPHASETRIG)
82
DPWM Phase Trigger Register (DPWMPHASETRIG) Register Field Descriptions
82
DPWM Cycle Adjust a Register (DPWMCYCADJA)
83
DPWM Cycle Adjust a Register (DPWMCYCADJA) Register Field Descriptions
83
DPWM Cycle Adjust B Register (DPWMCYCADJB)
84
DPWM Cycle Adjust B Register (DPWMCYCADJB) Register Field Descriptions
84
DPWM Resonant Duty Register (DPWMRESDUTY)
85
DPWM Resonant Duty Register (DPWMRESDUTY) Register Field Descriptions
85
DPWM Fault Control Register (DPWMFLTCTRL)
86
DPWM Fault Control Register (DPWMFLTCTRL) Register Field Descriptions
86
DPWM Overflow Register (DPWMOVERFLOW)
87
DPWM Overflow Register (DPWMOVERFLOW) Register Field Descriptions
87
DPWM Interrupt Register (DPWMINT)
88
DPWM Interrupt Register (DPWMINT) Register Field Descriptions
88
DPWM Counter Preset Register (DPWMCNTPRE)
90
DPWM Counter Preset Register (DPWMCNTPRE) Register Field Descriptions
90
DPWM Blanking a Begin Register (DPWMBLKABEG)
91
DPWM Blanking a Begin Register (DPWMBLKABEG) Register Field Descriptions
91
DPWM Blanking a End Register (DPWMBLKAEND)
92
DPWM Blanking a End Register (DPWMBLKAEND) Register Field Descriptions
92
DPWM Blanking B Begin Register (DPWMBLKBBEG)
93
DPWM Blanking B Begin Register (DPWMBLKBBEG) Register Field Descriptions
93
DPWM Blanking B End Register (DPWMBLKBEND)
94
DPWM Blanking B End Register (DPWMBLKBEND) Register Field Descriptions
94
DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI)
95
DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI) Register Field Descriptions
95
DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO)
96
DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO) Register Field Descriptions
96
DPWM Adaptive Sample Register (DPWMADAPTIVE)
97
DPWM Adaptive Sample Register (DPWMADAPTIVE) Register Field Descriptions
97
DPWM Fault Status (DPWMFLTSTAT)
98
DPWM Fault Status (DPWMFLTSTAT) Register Field Descriptions
98
DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH)
99
DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH) Register Field Descriptions
99
DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH)
100
DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH) Register Field Descriptions
100
DPWM Auto Switch Low Upper Thresh Register (DPWMAUTOSWLOUPTHRESH)
101
DPWM Auto Switch Low Upper Thresh Register (DPWMAUTOSWLOUPTHRESH) Register Field Descriptions
101
DPWM Auto Switch Low Lower Thresh Register (DPWMAUTOSWLOLOWTHRESH)
102
DPWM Auto Switch Low Lower Thresh Register (DPWMAUTOSWLOLOWTHRESH) Register Field Descriptions
102
DPWM Auto Config Max Register (DPWMAUTOMAX)
103
DPWM Auto Config Max Register (DPWMAUTOMAX) Register Field Descriptions
103
DPWM Auto Config MID Register (DPWMAUTOMID)
105
DPWM Auto Config MID Register (DPWMAUTOMID) Register Field Descriptions
105
DPWM Edge PWM Generation Control Register (DPWMEDGEGEN)
107
DPWM Edge PWM Generation Control Register (DPWMEDGEGEN) Register Field Descriptions
107
DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD)
109
DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD) Register Field Descriptions
109
DPWM bist Status Register (DPWMBISTSTAT)
110
DPWM bist Status Register (DPWMBISTSTAT) Register Field Descriptions
110
3 Front End
111
Simplified Block Diagram of Front End in UCD3138
111
112
Error ADC and Front End Gain
113
Front End Gain
113
EADC Error Output
113
EADC Triggering, EADC Output to Filter
115
EADC Timing
115
EADC Averaging
116
Consecutive Mode of Averaging by EADC
116
Spatial Mode of Averaging by EADC
116
Enabling EADC and Front End 3.2 Front End DAC
118
Front End DAC
118
Ramp Module
119
DAC Ramp Overview
119
DAC Ramp Start and End Points
119
DAC Ramp Steps
120
DAC Dither
120
DAC Ramp Start, Interrupts, Start Delay
121
RAMPSTAT Register
121
DAC RAMP When EADC Is Saturated
121
Using Ramp Module for Peak Current Mode
121
Sync FET Soft On/Off Using Ramp Module
122
Ideal Diode Emulation (IDE) Module in UCD3138
122
Successive Approximation Mode
123
SAR Control Parameters
123
SAR Algorithm Overview
123
Non-Continuous SAR Mode
123
Continuous SAR Mode
123
Absolute Value Without SAR
124
EADC Modes
124
Front End Control Registers
124
Ramp Control Register (RAMPCTRL)
124
Ramp Control Register (RAMPCTRL) Register Field Descriptions
124
Ramp Status Register (RAMPSTAT)
126
Ramp Status Register (RAMPSTAT) Register Field Descriptions
126
Ramp Cycle Register (RAMPCYCLE)
127
Ramp Cycle Register (RAMPCYCLE) Register Field Descriptions
127
EADC DAC Value Register (EADCDAC)
128
EADC DAC Value Register (EADCDAC) Register Field Descriptions
128
Ramp DAC Ending Value Register (RAMPDACEND)
129
Ramp DAC Ending Value Register (RAMPDACEND) Register Field Descriptions
129
DAC Step Register (DACSTEP)
130
DAC Step Register (DACSTEP) Register Field Descriptions
130
DAC Saturation Step Register (DACSATSTEP)
131
DAC Saturation Step Register (DACSATSTEP) Register Field Descriptions
131
EADC Trim Register (EADCTRIM) - (for Factory Test Use Only)
132
EADC Trim Register (EADCTRIM)
132
EADC Trim Register (EADCTRIM) Register Field Descriptions
132
EADC Control Register (EADCCTRL)
133
EADC Control Register (EADCCTRL) Register Field Descriptions
133
Analog Control Register (ACTRL) (for Test Use Only)
135
Analog Control Register (ACTRL)
135
Analog Control Register (ACTRL) Register Field Descriptions
135
Pre-Bias Control Register 0 (PREBIASCTRL0)
136
Pre-Bias Control Register 0 (PREBIASCTRL0) Register Field Descriptions
136
Pre-Bias Control Register 1 (PREBIASCTRL1)
137
Pre-Bias Control Register 1 (PREBIASCTRL1) Register Field Descriptions
137
SAR Control Register (SARCTRL)
138
SAR Control Register (SARCTRL) Register Field Descriptions
138
SAR Timing Register (SARTIMING)
139
SAR Timing Register (SARTIMING) Register Field Descriptions
139
EADC Value Register (EADCVALUE)
140
EADC Value Register (EADCVALUE) Register Field Descriptions
140
EADC Raw Value Register (EADCRAWVALUE)
141
EADC Raw Value Register (EADCRAWVALUE) Register Field Descriptions
141
DAC Status Register (DACSTAT)
142
DAC Status Register (DACSTAT) Register Field Descriptions
142
Filter
143
Filter Math Details
144
Proportional Branch
145
Add, Saturate, Scale and Clamp
146
Filter Output Stage
147
Filter Status Register
148
Filter Enable
149
Output Multiplier Select
150
Kcomp as Output Multiplier
151
XN, YN Read and Write Registers
152
Coefficient Configuration Register
153
Kp, Ki, and Kd Registers
155
Filter Status Register (FILTERSTATUS)
156
Clamp Registers
156
Filter Status Register (FILTERSTATUS) Register Field Descriptions
157
Filter Control Register (FILTERCTRL)
158
Filter Control Register (FILTERCTRL) Register Field Descriptions
158
CPU XN Register (CPUXN)
160
CPU XN Register (CPUXN) Register Field Descriptions
160
Filter XN Read Register (FILTERXNREAD)
161
Filter XN Read Register (FILTERXNREAD) Register Field Descriptions
161
Filter KI_YN Read Register (FILTERKIYNREAD)
162
Filter KI_YN Read Register (FILTERKIYNREAD) Register Field Descriptions
162
Filter KD_YN Read Register (FILTERKDYNREAD)
163
Filter KD_YN Read Register (FILTERKDYNREAD) Register Field Descriptions
163
Filter YN Read Register (FILTERYNREAD)
164
Filter YN Read Register (FILTERYNREAD) Register Field Descriptions
164
Coefficient Configuration Register (COEFCONFIG) Register Field Descriptions
165
Coefficient Configuration Register (COEFCONFIG)
167
Filter KP Coefficient 0 Register (FILTERKPCOEF0)
168
Filter KP Coefficient 0 Register (FILTERKPCOEF0) Register Field Descriptions
168
Filter KP Coefficient 1 Register (FILTERKPCOEF1)
169
Filter KP Coefficient 1 Register (FILTERKPCOEF1) Register Field Descriptions
169
Filter KI Coefficient 0 Register (FILTERKICOEF0)
170
Filter KI Coefficient 0 Register (FILTERKICOEF0) Register Field Descriptions
170
Filter KI Coefficient 1 Register (FILTERKICOEF1)
171
Filter KI Coefficient 1 Register (FILTERKICOEF1) Register Field Descriptions
171
Filter KD Coefficient 0 Register (FILTERKDCOEF0)
172
Filter KD Coefficient 0 Register (FILTERKDCOEF0) Register Field Descriptions
172
Filter KD Coefficient 1 Register (FILTERKDCOEF1)
173
Filter KD Coefficient 1 Register (FILTERKDCOEF1) Register Field Descriptions
173
Filter KD Alpha Register (FILTERKDALPHA)
174
Filter KD Alpha Register (FILTERKDALPHA) Register Field Descriptions
174
Filter Nonlinear Limit Register 0 (FILTERNL0)
175
Filter Nonlinear Limit Register 0 (FILTERNL0) Register Field Descriptions
175
Filter Nonlinear Limit Register 1 (FILTERNL1)
176
Filter Nonlinear Limit Register 1 (FILTERNL1) Register Field Descriptions
176
Filter Nonlinear Limit Register 2 (FILTERNL2)
177
Filter Nonlinear Limit Register 2 (FILTERNL2) Register Field Descriptions
177
Filter KI Feedback Clamp High Register (FILTERKICLPHI)
178
Filter KI Feedback Clamp High Register (FILTERKICLPHI) Register Field Descriptions
178
Filter KI Feedback Clamp Low Register (FILTERKICLPLO)
179
Filter KI Feedback Clamp Low Register (FILTERKICLPLO) Register Field Descriptions
179
Filter YN Clamp High Register (FILTERYNCLPHI)
180
Filter YN Clamp High Register (FILTERYNCLPHI) Register Field Descriptions
180
Filter YN Clamp Low Register (FILTERYNCLPLO)
181
Filter YN Clamp Low Register (FILTERYNCLPLO) Register Field Descriptions
181
Filter Output Clamp High Register (FILTEROCLPHI)
182
Filter Output Clamp High Register (FILTEROCLPHI) Register Field Descriptions
182
Filter Output Clamp Low Register (FILTEROCLPLO)
183
Filter Output Clamp Low Register (FILTEROCLPLO) Register Field Descriptions
183
Filter Preset Register (FILTERPRESET)
184
Filter Preset Register (FILTERPRESET) Register Field Descriptions
184
5 Loop Mux
185
186
External DAC Control (EXTDACCTRL)
187
Front End Control Muxes (FECTRL0MUX, FECTRL1MUX, FECTRL2MUX)
187
Sample Trigger Control (SAMPTRIGCTRL)
187
DPWM Mux Register (DPWMMUX)
188
Filter Kcomp Registers (Filterkcompx)
188
Filter Mux Register (FILTERMUX)
188
Global Enable Register (GLBEN)
188
5.10 Light Load (Burst) Mode
189
5.11 Constant Current / Constant Power
189
PWM Global Period Register (PWMGLBPRD)
189
Sync Control (SYNCCTRL)
189
UCD3138 Flux Balancing Approach
190
5.12 Analog Peak Current Mode
190
5.13 Automatic Cycle Adjustment
190
Front End Control 0 Mux Register (FECTRL0MUX)
191
Front End Control 0 Mux Register (FECTRL0MUX) Register Field Descriptions
191
5.14 Loop Mux Registers Reference
191
Configuration
191
Front End Control 1 Mux Register (FECTRL1MUX)
193
Front End Control 1 Mux Register (FECTRL1MUX) Register Field Descriptions
193
Front End Control 2 Mux Register (FECTRL2MUX)
195
Front End Control 2 Mux Register (FECTRL2MUX) Register Field Descriptions
195
Sample Trigger Control Register (SAMPTRIGCTRL)
197
Sample Trigger Control Register (SAMPTRIGCTRL) Register Field Descriptions
197
External DAC Control Register (EXTDACCTRL)
198
External DAC Control Register (EXTDACCTRL) Register Field Descriptions
198
Filter Mux Register (FILTERMUX)
199
Filter Mux Register (FILTERMUX) Register Field Descriptions
199
Filter Kcomp a Register (FILTERKCOMPA)
201
Filter Kcomp a Register (FILTERKCOMPA) Register Field Descriptions
201
Filter Kcomp B Register (FILTERKCOMPB)
202
Filter Kcomp B Register (FILTERKCOMPB) Register Field Descriptions
202
DPWM Mux Register (DPWMMUX)
203
DPWM Mux Register (DPWMMUX) Register Field Descriptions
203
Constant Power Control Register (CPCTRL)
205
Constant Power Control Register (CPCTRL) Register Field Descriptions
205
Constant Power Nominal Threshold Register (CPNOM)
207
Constant Power Nominal Threshold Register (CPNOM) Register Field Descriptions
207
Constant Power Max Threshold Register (CPMAX)
208
Constant Power Max Threshold Register (CPMAX) Register Field Descriptions
208
Constant Power Configuration Register (CPCONFIG)
209
Constant Power Configuration Register (CPCONFIG) Register Field Descriptions
209
Constant Power Max Power Register (CPMAXPWR)
210
Constant Power Max Power Register (Cpmaxpwr)Register Field Descriptions
210
Constant Power Integrator Threshold Register (CPINTTHRESH)
211
Constant Power Integrator Threshold Register (CPINTTHRESH) Register Field Descriptions
211
Constant Power Firmware Divisor Register (CPFWDIVISOR)
212
Constant Power Firmware Divisor Register (CPFWDIVISOR) Register Field Descriptions
212
Onstant Power Status Register (CPSTAT)
213
Onstant Power Status Register (CPSTAT) Register Field Descriptions
213
Cycle Adjustment Control Register (CYCADJCTRL)
214
Cycle Adjustment Control Register (CYCADJCTRL) Register Field Descriptions
214
Cycle Adjustment Limit Register (CYCADJLIM)
215
Cycle Adjustment Limit Register (CYCADJLIM) Register Field Descriptions
215
Cycle Adjustment Status Register (CYCADJSTAT)
216
Cycle Adjustment Status Register (CYCADJSTAT) Register Field Descriptions
216
Global Enable Register (GLBEN)
217
PWM Global Period Register (PWMGLBPRD)
218
PWM Global Period Register (PWMGLBPRD) Register Field Descriptions
218
Sync Control Register (SYNCCTRL)
219
Sync Control Register (SYNCCTRL) Register Field Descriptions
219
Light Load Control Register (LLCTRL)
220
Light Load Control Register (LLCTRL) Register Field Descriptions
220
Light Load Enable Threshold Register (LLENTHRESH)
221
Light Load Enable Threshold Register (LLENTHRESH) Register Field Descriptions
221
Light Load Disable Threshold Register (LLDISTHRESH)
222
Light Load Disable Threshold Register (LLDISTHRESH) Register Field Descriptions
222
Peak Current Mode Control Register (PCMCTRL)
223
Peak Current Mode Control Register (PCMCTRL) Register Field Descriptions
223
Analog Peak Current Mode Control Register (APCMCTRL)
224
Analog Peak Current Mode Control Register (Apcmctrl)Register Field Descriptions
224
Loop Mux Test Register (LOOPMUXTEST) (Test Use Only)
225
Loop Mux Test Register (LOOPMUXTEST) (Test Use Only) Register Field Descriptions
225
6 Fault Mux
226
UCD3138 Fault Handling System
226
227
UCD3138 Analog Comparator Control
228
Analog Comparator Configuration
228
Analog Comparator Ramp
229
Digital Comparator Configuration
229
Acomp_F_Ref_Sel
229
Fault Pin Configuration
230
Analog Peak Current
230
Fault Status Registers
230
Fault Mux Control Registers
230
UCD3138 DPWM Fault Action
231
DPWM Fault Action
231
IDE / DCM Detection Control
232
6.10 Oscillator Failure Detection
234
6.11 Fault Mux Registers Reference
234
Analog Comparator Control 0 Register (ACOMPCTRL0)
235
Analog Comparator Control 0 Register (ACOMPCTRL0) Register Field Descriptions
235
Analog Comparator Control 1 Register (ACOMPCTRL1)
237
Analog Comparator Control 1 Register (ACOMPCTRL1) Register Field Descriptions
237
Analog Comparator Control 2 Register (ACOMPCTRL2)
239
Analog Comparator Control 2 Register (ACOMPCTRL2) Register Field Descriptions
239
Analog Comparator Control 3 Register (ACOMPCTRL3)
241
Analog Comparator Control 3 Register (ACOMPCTRL3) Register Field Descriptions
241
External Fault Control Register (EXTFAULTCTRL)
242
External Fault Control Register (EXTFAULTCTRL) Register Field Descriptions
242
Fault Mux Interrupt Status Register (FAULTMUXINTSTAT)
243
Fault Mux Interrupt Status Register (FAULTMUXINTSTAT) Register Field Descriptions
243
Fault Mux Raw Status Register (FAULTMUXRAWSTAT)
245
Fault Mux Raw Status Register (FAULTMUXRAWSTAT) Register Field Descriptions
245
Comparator Ramp Control 0 Register (COMPRAMP0)
247
Comparator Ramp Control 0 Register (COMPRAMP0) Register Field Descriptions
247
Digital Comparator Control 0 Register (DCOMPCTRL0)
249
Digital Comparator Control 0 Register (DCOMPCTRL0) Register Field Descriptions
249
Digital Comparator Control 1 Register (DCOMPCTRL1)
250
Digital Comparator Control 1 Register (DCOMPCTRL1) Register Field Descriptions
250
Digital Comparator Control 2 Register (DCOMPCTRL2)
251
Digital Comparator Control 2 Register (DCOMPCTRL2) Register Field Descriptions
251
Digital Comparator Control 3 Register (DCOMPCTRL3)
252
Digital Comparator Control 3 Register (DCOMPCTRL3) Register Field Descriptions
252
Digital Comparator Counter Status Register (DCOMPCNTSTAT)
253
Digital Comparator Counter Status Register (DCOMPCNTSTAT) Register Field Descriptions
253
DPWM 0 Current Limit Control Register (DPWM0CLIM)
254
DPWM 0 Current Limit Control Register (DPWM0CLIM) Register Field Descriptions
254
DPWM 0 Fault AB Detection Register (DPWM0FLTABDET)
256
DPWM 0 Fault AB Detection Register (DPWM0FLTABDET) Register Field Descriptions
256
DPWM 0 Fault Detection Register (DPWM0FAULTDET)
257
DPWM 0 Fault Detection Register (DPWM0FAULTDET) Register Field Descriptions
257
DPWM 1 Current Limit Control Register (DPWM1CLIM)
260
DPWM 1 Current Limit Control Register (DPWM1CLIM) Register Field Descriptions
260
DPWM 1 Fault AB Detection Register (DPWM1FLTABDET)
262
DPWM 1 Fault AB Detection Register (DPWM1FLTABDET) Register Field Descriptions
262
DPWM 1 Fault Detection Register (DPWM1FAULTDET)
264
DPWM 1 Fault Detection Register (DPWM1FAULTDET) Register Field Descriptions
264
DPWM 2 Current Limit Control Register (DPWM2CLIM)
267
DPWM 2 Current Limit Control Register (DPWM2CLIM) Register Field Descriptions
267
DPWM 2 Fault AB Detection Register (DPWM2FLTABDET)
269
DPWM 2 Fault AB Detection Register (DPWM2FLTABDET) Register Field Descriptions
269
DPWM 2 Fault Detection Register (DPWM2FAULTDET)
271
DPWM 2 Fault Detection Register (DPWM2FAULTDET) Register Field Descriptions
271
DPWM 3 Current Limit Control Register (DPWM3CLIM)
274
DPWM 3 Current Limit Control Register (DPWM3CLIM) Register Field Descriptions
274
DPWM 3 Fault AB Detection Register (DPWM3FLTABDET)
276
DPWM 3 Fault AB Detection Register (DPWM3FLTABDET) Register Field Descriptions
276
DPWM 3 Fault Detection Register (DPWM3FAULTDET)
278
DPWM 3 Fault Detection Register (DPWM3FAULTDET) Register Field Descriptions
278
HFO Fail Detect Register (HFOFAILDET)
281
HFO Fail Detect Register (HFOFAILDET) Register Field Descriptions
281
LFO Fail Detect Register (LFOFAILDET)
282
LFO Fail Detect Register (LFOFAILDET) Register Field Descriptions
282
IDE Control Register (IDECTRL)
283
IDE Control Register (IDECTRL) Register Field Descriptions
283
Gio Module
284
Fault IO Direction Register (FAULTDIR)
285
Fault IO Direction Register (FAULTDIR) Register Field Descriptions
285
Fault Input Register (FAULTIN)
286
Fault Input Register (FAULTIN) Register Field Descriptions
286
Fault Output Register (FAULTOUT)
287
Fault Output Register (FAULTOUT) Register Field Descriptions
287
Fault Interrupt Enable Register (FAULTINTENA)
288
Fault Interrupt Enable Register (FAULTINTENA) Register Field Descriptions
288
Fault Interrupt Polarity Register (FAULTINTPOL)
289
Fault Interrupt Polarity Register (FAULTINTPOL) Register Field Descriptions
289
Fault Interrupt Pending Register (FAULTINTPEND)
290
Fault Interrupt Pending Register (FAULTINTPEND) Register Field Descriptions
290
External Interrupt Direction Register (EXTINTDIR)
291
External Interrupt Direction Register (EXTINTDIR) Register Field Descriptions
291
External Interrupt Input Register (EXTINTIN)
292
External Interrupt Input Register (EXTINTIN) Register Field Descriptions
292
External Interrupt Output Register (EXTINTOUT)
293
External Interrupt Output Register (EXTINTOUT) Register Field Descriptions
293
External Interrupt Enable Register (EXTINTENA)
294
External Interrupt Enable Register (EXTINTENA) Register Field Descriptions
294
External Interrupt Polarity Register (EXTTINTPOL)
295
External Interrupt Polarity Register (EXTTINTPOL) Register Field Descriptions
295
External Interrupt Pending Register (EXTINTPEND)
296
External Interrupt Pending Register (EXTINTPEND) Register Field Descriptions
296
7.13 References
296
8 ADC12 Overview
297
ADC12 Control Block Diagram
297
298
ADC Input Impedance Model Containing External Circuits
299
ADC12 Input Impedance Model
299
ADC12 Channel Impedance
300
ADC12 Impedance Vs. Sampling Frequency Data
300
Impedance Test Setup
300
Channel to Channel Crosstalk
301
Effect of External Capacitance
301
External Capacitance Makes Lower Source Impedance
301
S/H Capacitor Charge Vs. Settling Time
301
ADC Control Register (ADCCTRL)
302
ADC12 Control FSM
302
Conversion
302
Impedance Roll-Off Due to Crosstalk
302
Sequencing
303
UCS3138 Digital Comparators Control Block Diagram
304
Digital Comparators
304
8.10 ADC Averaging
305
8.11 Temperature Sensor
305
Temp Sensor Control Register (TEMPSENCTRL)
306
Temp Sensor Control Register (TEMPSENCTRL) Register Field Descriptions
306
Pmbus Control Register 3 (PMBCTRL3)
307
Pmbus Control Register 3 (PMBCTRL3) Register Field Descriptions
307
Pmbus Addressing
307
Pmbus Addressing
308
Selection of "Dual Sample and Hold" Channel
308
8.14 Dual Sample and Hold
308
ADC Control Register (ADCCTRL)
309
ADC Control Register (ADCCTRL) Register Field Descriptions
309
8.15 Usage of Sample and Hold Circuitry for High Impedance Measurement
309
ADC12 Dual Sample and Hold Configuration
310
ADC Configuration Examples
311
C Code Example
311
Single Sweep Operation
312
Auto-Triggered Conversions
313
Start/Stop Operation (External Trigger)
314
Dual Sample and Hold Circuitry in ADC12
310
8.17 Useful C Language Statement Examples
315
ADC Control Register (ADCCTRL)
316
ADC Control Register (ADCCTRL) Register Field Descriptions
316
ADC Registers
316
ADC Control Register (ADCCTRL) Register Field Descriptions
317
ADC Status Register (ADCSTAT)
318
ADC Status Register (ADCSTAT) Register Field Descriptions
318
ADC Test Control Register (ADCTSTCTRL)
319
ADC Test Control Register (ADCTSTCTRL) Register Field Descriptions
319
ADC Sequence Select Register 0 (ADCSEQSEL0)
320
ADC Sequence Select Register 0 (ADCSEQSEL0) Register Field Descriptions
320
ADC Sequence Select Register 1 (ADCSEQSEL1)
321
ADC Sequence Select Register 1 (ADCSEQSEL1) Register Field Descriptions
321
ADC Sequence Select Register 2 (ADCSEQSEL2)
322
ADC Sequence Select Register 2 (ADCSEQSEL2) Register Field Descriptions
322
ADC Sequence Select Register 3 (ADCSEQSEL3)
323
ADC Sequence Select Register 3 (ADCSEQSEL3) Register Field Descriptions
323
ADC Result Registers 0-15 (Adcresultx, X=0:15)
324
ADC Result Registers 0-15 (Adcresultx, X=0:15) Register Field Descriptions
324
ADC Averaged Result Registers 0-5 (Adcavgresultx, X=0:15)
325
ADC Averaged Result Registers 0-5 (Adcavgresultx, X=0:15) Register Field Descriptions
325
ADC Digital Compare Limits Register 0-5 (Adccomplimx, X=0:5)
326
ADC Digital Compare Limits Register 0-5 (Adccomplimx, X=0:5) Register Field Descriptions
326
ADC Digital Compare Enable Register (ADCCOMPEN)
327
ADC Digital Compare Enable Register (ADCCOMPEN) Register Field Descriptions
327
ADC Digital Compare Results Register (ADCCOMPRESULT)
329
ADC Digital Compare Results Register (ADCCOMPRESULT) Register Field Descriptions
329
ADC Averaging Control Register (ADCAVGCTRL)
331
ADC Averaging Control Register (ADCAVGCTRL) Register Field Descriptions
331
9 Advanced Power Management Control Functions
333
Package ID Information
334
Tolerance
335
Package ID Register (PKGID)
336
Package ID Register (PKGID) Register Field Descriptions
336
Temperature Reference
336
Brownout Register (BROWNOUT)
337
Brownout Register (BROWNOUT) Register Field Descriptions
337
Temp Sensor Control Register (TEMPSENCTRL)
338
Temp Sensor Control Register (TEMPSENCTRL) Register Field Descriptions
338
Control
339
I/O Mux Control Register (IOMUX)
339
Bits 9-8: EXT_TRIG_MUX_SEL - EXT_TRIG Pin Mux Select
339
Bits 7-6: JTAG_CLK_MUX_SEL - TCK Pin Mux Select
339
Bits 5-4: JTAG_DATA_MUX_SEL - TDO/TDI Pin Mux Select
339
Bits 3-2: SYNC_MUX_SEL - SYNC Pin Mux Select
339
Bit 1: UART_MUX_SEL - SCL/SDA Pins Mux Select
339
Bit 0: PMBUS_MUX_SEL - SCL/SDA Pins Mux Select
339
Current Sharing Control Register (CSCTRL)
340
Current Sharing Control Register (CSCTRL) Register Field Descriptions
340
Temperature Reference Register (TEMPREF)
341
Temperature Reference Register (TEMPREF) Register Field Descriptions
341
Power Disable Control Register (PWRDISCTRL)
342
Power Disable Control Register (PWRDISCTRL) Register Field Descriptions
342
GPIO Overview
343
Interaction with a Single Pin
344
Interaction with Multiple Pins
345
Global I/O en Register (GBIOEN)
346
Registers
346
Global I/O OE Register (GLBIOOE)
347
Global I/O OE Register (GLBIOOE) Register Field Descriptions
347
Global I/O Open Drain Control Register (GLBIOOD)
348
Global I/O Open Drain Control Register (GLBIOOD) Register Field Descriptions
348
Global I/O Value Register (GLBIOVAL)
349
Global I/O Value Register (GLBIOVAL) Register Field Descriptions
349
Global I/O Read Register (GLBIOREAD)
350
Global I/O Read Register (GLBIOREAD) Register Field Descriptions
350
Clock Trim Register (CLKTRIM) (for Factory Test Use Only, Except HFO_LN_FILTER_EN) Register
351
Trim and Test Registers - Note
351
10 Pmbus Interface/I2C Interface
352
Pmbus Register Summary
353
Initialization for I2C
354
Pmbus Slave Mode Command Examples
355
Command with PEC
357
Write Command and Byte - no PEC
357
Other Simple Writes with Auto Acknowledge
357
Write Command and Byte - with PEC
358
Write 2 Bytes with no PEC
358
Quick Command Write
358
Timing Diagram
359
Write 4 Bytes + Command
359
Slave Address Manual ACK for Write
360
Writes with Less than 3 Bytes Auto-Acknowledged
360
Manual ACK Command
361
Simple Read with Full Automation
362
Simple Read of 4 Bytes with Full Automation
363
Simple Read of 5 Bytes with Full Automation
363
Slave Address Manual ACK on a Read Address
364
Quick Command Read
364
Write/Read with Repeated Start
365
Automatic PEC Addition
366
Clock Stretch Timing for Read
367
Avoiding Clock Stretching
367
Alert Response
368
Address Byte Timing
369
Repeated Start Timing
369
Pmbus Slave Mode Low Level Timing
369
Read Byte Timing
370
Write Byte Timing
370
Write Byte Stop Timing
370
Timing Parameters from Timing Diagrams
371
Simple Timing Parameters (no Timing Diagram)
371
Effect of MAN_SLAVE_ACK Bit on EOM Handling
371
Master Mode Operation Reference
372
Quick Command Format
373
Send Byte W/O PEC Byte
373
Send Byte with PEC Byte
373
Receive Byte W/O PEC Byte
373
Receive Byte with PEC Byte
373
Write Byte W/O PEC Byte
374
Write Byte with PEC Byte
374
Write Word W/O PEC Byte
374
Write Word with PEC Byte
374
Read Byte W/O PEC Byte
375
Read Byte with PEC Byte
375
Read Word W/O PEC Byte
375
Read Word with PEC Byte
375
Process Call W/O PEC Byte
376
Process Call with PEC Byte
376
Block Write W/O PEC Byte
377
Block Write with PEC Byte
377
Block Read W/O PEC Byte
378
Block Read with PEC Byte
378
Block Write-Block Read Process Call W/O PEC Byte
379
Block Write-Block Read Process Call with PEC Byte
379
Alert Response
379
Extended Command Write Byte W/O PEC Byte
380
Extended Command Write Byte with PEC Byte
380
Extended Command Write Word W/O PEC Byte
380
Extended Command Write Word with PEC Byte
380
Extended Command Read Byte W/O PEC Byte
380
Extended Command Read Byte with PEC Byte
380
Extended Command Read Word W/O PEC Byte
380
Extended Command Read Word with PEC Byte
380
Group Command
381
PMBUS Control Register 1 (PMBCTRL1)
382
PMBUS Control Register 1 (PMBCTRL1) Register Field Descriptions
382
Test Mode (Manufacturer Reserved Address Match)
382
Pmbus Transmit Data Buffer (PMBTXBUF)
384
Pmbus Transmit Data Buffer (PMBTXBUF) Register Field Descriptions
384
Pmbus Receive Data Register (PMBRXBUF)
385
Pmbus Receive Data Register (PMBRXBUF) Register Field Descriptions
385
Pmbus Acknowledge Register (PMBACK)
386
Pmbus Acknowledge Register (PMBACK) Register Field Descriptions
386
Pmbus Status Register (PMBST)
387
Pmbus Status Register (PMBST) Register Field Descriptions
387
Pmbus Interrupt Mask Register (PMBINTM)
389
Pmbus Interrupt Mask Register (PMBINTM) Register Field Descriptions
389
Pmbus Control Register 2 (PMBCTRL2)
390
Pmbus Control Register 2 (PMBCTRL2) Register Field Descriptions
390
Pmbus Hold Slave Address Register (PMBHSA)
392
Pmbus Hold Slave Address Register (PMBHSA) Register Field Descriptions
392
Pmbus Control Register 3 (PMBCTRL3)
393
Pmbus Control Register 3 (PMBCTRL3) Register Field Descriptions
393
11 Timer Module Overview
396
T24 – 24 Bit Free-Running Timer with Capture and Compare
397
T24 Capture Block
398
T24 Compare Blocks
399
T16Pwmx Prescaler and Counter
400
T16 Shadow Bit
401
Using the T16 for a Timer Interrupt
402
Watchdog Prescale and Counter
403
Watchdog Timer Example
404
24-Bit Counter Data Register (T24CNTDAT)
405
Timer Module Register Reference
405
24-Bit Counter Control Register (T24CNTCTRL)
406
24-Bit Capture Channel Data Register (T24CAPDAT)
407
Bit Capture Channel Control Register (T24Capctrlx or T24CAPCTRL
408
24-Bit Capture I/O Control and Data Register (T24CAPIO)
409
24-Bit Output Compare Channel 0 Data Register (T24CMPDAT0)
410
24-Bit Output Compare Channel 1 Data Register (T24CMPDAT1)
411
24-Bit Output Compare Channel 0 Control Register (T24CMPCTRL0)
412
24-Bit Output Compare Channel 1 Control Register (T24CMPCTRL1)
413
Pwmx Counter Data Register (T16Pwmxcntdat)
414
Pwmx Counter Data Register (T16Pwmxcntdat) Register Field Descriptions
414
Pwmx Counter Control Register (T16Pwmxcntctrl)
415
Pwmx Counter Control Register (T16Pwmxcntctrl) Register Field Descriptions
415
Pwmx 16-Bit Compare Channel 0-1 Data Register (T16Pwmxcmpydat)
416
Pwmx 16-Bit Compare Channel 0-1 Data Register (T16Pwmxcmpydat) Register Field Descriptions
416
Pwmx Compare Control Register (T16Pwmxcmpctrl)
417
Pwmx Compare Control Register (T16Pwmxcmpctrl) Register Field Descriptions
417
Watchdog Status (WDST)
419
Watchdog Status (WDST) Register Field Descriptions
419
Watchdog Control (WDCTRL)
420
Watchdog Control (WDCTRL) Register Field Descriptions
420
12 UART Overview
421
UART Frame Format
422
UART Interrupts
423
Transmit Interrupt
424
UART Control Register 0 (UARTCTRL0)
426
UART Control Register 0 (UARTCTRL0) Register Field Descriptions
426
UART Registers Reference
426
UART Receive Status Register (UARTRXST)
427
UART Receive Status Register (UARTRXST) Register Field Descriptions
427
UART Transmit Status Register (UARTTXST)
428
UART Transmit Status Register (UARTTXST) Register Field Descriptions
428
UART Control Register 3 (UARTCTRL3)
429
UART Control Register 3 (UARTCTRL3) Register Field Descriptions
429
UART Interrupt Status Register (UARTINTST)
430
UART Interrupt Status Register (UARTINTST) Register Field Descriptions
430
UART Baud Divisor High Byte Register (UARTHBAUD)
431
UART Baud Divisor High Byte Register (UARTHBAUD) Register Field Descriptions
431
UART Baud Divisor Middle Byte Register (UARTMBAUD)
432
UART Baud Divisor Middle Byte Register (UARTMBAUD) Register Field Descriptions
432
UART Baud Divisor Low Byte Register (UARTLBAUD)
433
UART Baud Divisor Low Byte Register (UARTLBAUD) Register Field Descriptions
433
UART Receive Buffer (UARTRXBUF)
434
UART Receive Buffer (UARTRXBUF) Register Field Descriptions
434
UART Transmit Buffer (UARTTXBUF)
435
UART Transmit Buffer (UARTTXBUF) Register Field Descriptions
435
UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX, UARTIOCTRLTX)
436
UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX, UARTIOCTRLTX) Register Field Descriptions
436
13 Boot ROM and Boot Flash
437
Boot ROM Function
438
UCD3138 Boot ROM Execution after Power-On/Reset
439
Boot Flash
440
Avoiding Program Flash Lockup
440
Using BOOT ROM Pmbus Interface
441
Read 4 Bytes
442
ROM Version for the Other Members of the UCD3138 Family
443
Memory Write Functionality
443
Write Next 16 Bytes
444
Boot ROM Mass Erase Data Byte Parameter Values
445
Page Erase
445
Boot ROM Execute Flash Command Byte, Valid Values
446
Checksum Functions
447
UCD3138064 Boot ROM Execution after Power-On/Reset
448
Checksums Used by UCD3138064 Boot ROM Program
448
Boot ROM for the Other Members of the UCD3138 Family
448
Checksums Used by UCD3138A64 Boot ROM Program
449
UCD3138A64 and UCD3138A64A
449
UCD3138A64 Boot ROM Execution after Power-On/Reset
450
Checksums Used by UCD3138128 Boot ROM Program
450
UCD3138128 and UCD3138128A
450
UCD3138128 Boot ROM Execution after Power-On/Reset
451
14 Arm7Tdmi-S Mpuss
452
ARM Processor Operating Modes
453
General-Purpose Registers and Program Counter
453
ARM7TDMI-S Modes of Operation
453
Current Program Status Register
454
Bit Patterns in Different ARM Processor Operating Modes
454
ARM Processor Exceptions
455
Fast Interrupt (FIQ)
456
ARM7TDMI-S Instruction Set
457
Level of Dual-State Support
458
Implementation
459
UCD3138 Reference Code
461
ROM and Program Flash Memory Map (ROM Operation)
465
Memory
465
Memory Map (Flash Operation)
466
RAM and Data Flash Memory Map (ROM and Flash Operation)
466
Memory Map (System and Peripherals Blocks)
466
Static Memory Control Register (SMCTRL)
468
Static Memory Control Register (SMCTRL) Register Field Descriptions
468
Memory Controller – MMC Registers Reference
468
Write Control Register (WCTRL)
470
Write Control Register (WCTRL) Register Field Descriptions
470
Peripheral Control Register (PCTRL)
471
Peripheral Control Register (PCTRL) Register Field Descriptions
471
Peripheral Location Register (PLOC)
472
Peripheral Location Register (PLOC) Register Field Descriptions
472
Peripheral Protection Register (PPROT)
473
Peripheral Protection Register (PPROT) Register Field Descriptions
473
Memory Fine Base Address High Register 0 (MFBAHR0)
474
Memory Fine Base Address High Register 0 (MFBAHR0) Register Field Descriptions
474
Memory Fine Base Address Low Register 0 (MFBALR0)
475
Memory Fine Base Address Low Register 0 (MFBALR0) Register Field Descriptions
475
Memory Fine Base Address High Register 1-3,17-19 (Mfbahrx)
476
Memory Fine Base Address High Register 1-3, 17-19 (Mfbahrx) Register Field Descriptions
476
Memory Fine Base Address Low Register 1-3, 17-19 (Mfbalrx)
477
Memory Fine Base Address Low Register 1-3, 17-19 (Mfbalrx) Register Field Descriptions
477
Memory Fine Base Address High Load Differences for Enhanced 3138 Devices
478
Memory Fine Base Address High Register 4 (MFBAHR4)
479
Memory Fine Base Address High Register 4 (MFBAHR4) Register Field Descriptions
479
Memory Fine Base Address Low Register 4-16 (Mfbalrx)
480
Memory Fine Base Address Low Register 4-17 (Mfbalrx) Register Field Descriptions
480
Memory Fine Base Address High Register 5 (MFBAHR5)
481
Memory Fine Base Address High Register 5 (MFBAHR5) Register Field Descriptions
481
Memory Fine Base Address High Register 6 (MFBAHR6)
482
Memory Fine Base Address High Register 6 (MFBAHR6) Register Field Descriptions
482
Memory Fine Base Address High Register 7 (MFBAHR7)
483
Memory Fine Base Address High Register 7 (MFBAHR7) Register Field Descriptions
483
Memory Fine Base Address High Register 8 (MFBAHR8)
484
Memory Fine Base Address High Register 8 (MFBAHR8) Register Field Descriptions
484
Memory Fine Base Address High Register 9 (MFBAHR9)
485
Memory Fine Base Address High Register 9 (MFBAHR9) Register Field Descriptions
485
Memory Fine Base Address High Register 10 (MFBAHR10)
486
Memory Fine Base Address High Register 10 (MFBAHR10) Register Field Descriptions
486
Memory Fine Base Address High Register 11 (MFBAHR11)
487
Memory Fine Base Address High Register 11 (MFBAHR11) Register Field Descriptions
487
Memory Fine Base Address High Register 12 (MFBAHR12)
488
Memory Fine Base Address High Register 12 (MFBAHR12) Register Field Descriptions
488
Memory Fine Base Address High Register 13 (MFBAHR13)
489
Memory Fine Base Address High Register 13 (MFBAHR13) Register Field Descriptions
489
Memory Fine Base Address High Register 14 (MFBAHR14)
490
Memory Fine Base Address High Register 14 (MFBAHR14) Register Field Descriptions
490
Memory Fine Base Address High Register 15 (MFBAHR15)
491
Memory Fine Base Address High Register 15 (MFBAHR15) Register Field Descriptions
491
Memory Fine Base Address High Register 16 (MFBAHR16)
492
Memory Fine Base Address High Register 16 (MFBAHR16) Register Field Descriptions
492
Program Flash Control Register (PFLASHCTRL)
493
PFLASHCTRL Addresses
493
Program Flash Control Register (PFLASHCTRL) Register Field Descriptions
493
Data Flash Control Register (DFLASHCTRL)
494
Data Flash Control Register (DFLASHCTRL) Register Field Descriptions
494
Flash Interlock Register (FLASHILOCK)
495
Flash Interlock Register (FLASHILOCK) Register Field Descriptions
495
16 Control System Module
496
Address Decoder (DEC)
497
Base Address
499
Why Change Memory Map
499
Erasing the Programming Flash
500
Flash Interlock Register
501
Erasing Program Flash
502
Interrupt Priority Table
503
Interrupt Handling by CPU
504
CIM Input Channel Management
505
CIM Prioritization
506
Clock Control Register (CLKCNTL)
508
Clock Control Register (CLKCNTL) Register Field Descriptions
508
Register Map
508
System Exception Control Register (SYSECR)
510
System Exception Control Register (SYSECR) Register Field Descriptions
510
System Exception Status Register (SYSESR)
511
System Exception Status Register (SYSESR) Register Field Descriptions
511
Abort Exception Status Register (ABRTESR)
513
Abort Exception Status Register (ABRTESR) Register Field Descriptions
513
Global Status Register (GLBSTAT)
514
Global Status Register (GLBSTAT) Register Field Descriptions
514
Device Identification Register (DEV)
515
Device Identification Register (DEV) Register Field Descriptions
515
System Software Interrupt Flag Register (SSIF)
516
System Software Interrupt Flag Register (SSIF) Register Field Descriptions
516
System Software Interrupt Request Register (SSIR)
517
System Software Interrupt Request Register (SSIR) Register Field Descriptions
517
17 Flash Memory Programming, Integrity, and Security
518
Quick Start Summary
519
Flash Programming in ROM Mode
520
Flash Management for Firmware Development
521
Communications Backdoors
522
Firmware Examples
523
Erasing Flash
524
18 CIM – Central Interrupt Module Registers Reference
525
IRQ Index Offset Vector Register (IRQIVEC)
526
IRQ Index Offset Vector Register (IRQIVEC) Register Field Descriptions
526
FIQ Index Offset Vector Register (FIQIVEC)
527
FIQ Index Offset Vector Register (FIQIVEC) Register Field Descriptions
527
FIQ/IRQ Program Control Register (FIRQPR)
528
Pending Interrupt Read Location Register (INTREQ)
529
Interrupt Mask Register (REQMASK)
530
Revision History
531
Important Notice
532
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Texas Instruments UCD3138 User Manual (64 pages)
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 3 MB
Table of Contents
Typical Applications
4
Electrical Performance Specifications
5
Test Equipment
8
Recommended Test Setup
8
List of Test Points
10
List of Terminals
10
Test Procedure
11
Equipment Shutdown
11
Performance Data and Typical Characteristic Curves
12
Power Factor
12
Output Voltage Ripple
15
Total Harmonic Distortion (THD)
17
EVM Assembly Drawing and PCB Layout
19
List of Materials
22
State Machine
39
System Protection
40
Graphical User Interface (GUI)
45
Evaluation Board/Kit/Module (Evm) Additional Terms
56
Regulatory Compliance Information
56
Evaluation Board/Kit/Module (Evm) Warnings, Restrictions and Disclaimers
59
Important Notice
64
Texas Instruments UCD3138 User Manual (21 pages)
Practical Design Guideline
Brand:
Texas Instruments
| Category:
Controller
| Size: 3 MB
Table of Contents
Table of Contents
2
List of Figures
3
Introduction
4
UCD3138 Pin Connection Recommendation
5
Reset Pin
5
ADC Pins
5
Reset Pin Connection
5
EAP and EAN Pins
6
Current Amplifier with EADC Connection
6
UART Communication Port
6
Local Filter on Eapx/Eanx Pins
6
Current Amplifier Connected with EADC
6
Dpwm Pins
7
Gpios
7
Termination for Communication Port (UART)
7
Clamping Diodes for DPWM
7
Bias Supply and Grounding
8
Clamping Diodes for GPIO
8
V and Ground Connection Diagram for UCD3138A (64-Pin)
8
V and Ground Connection Diagram for UCD3138 (64-Pin)
9
V and Ground Connection Diagram for UCD3138A (40-Pin)
9
Bp18
10
Layout Example for UCD3138ARGC by Using a Single Ground
10
Layout Example for UCD3138ARGC on Top Layer
11
Layout Example for UCD3138ARGC on Internal Ground Layer
11
Layout Example for UCD3138ARGC by Using a Single Ground
12
Layout Example for UCD3138A (40-Pin) on Top Layer
12
Layout Example for UCD3138A (40-Pin) on Internal Ground Layer
12
Layout Example for UCD3138128A by Using a Single Ground
13
Layout Example for UCD3138128A on Top Layer
13
Layout Example for UCD3138128A on Internal Ground Layer
13
DPWMS Synchronization
14
External Clock
14
EMI/EMC Mitigation Guideline
15
Optional Ground Layer Assignment
15
Special Consideration
16
Single Ground Plane for a Power Module Design
16
Important Notice
21
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