Dpwm Mux Register (Dpwmmux); Dpwm Mux Register (Dpwmmux) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

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5.14.9 DPWM Mux Register (DPWMMUX)

Address 00020020
31 30
DPWM3_SYNC_FET_SEL
R/W-00
23 22
Reserved
15 14
DPWM1_SYNC_SEL
R/W-00
7 6
DPWM2_FILTER_SEL
R/W-010
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-10. DPWM Mux Register (DPWMMUX) Register Field Descriptions
Bit Field
31-30 DPWM3_SYNC
_FET_SEL
29-28 DPWM2_SYNC
_FET_SEL
27-26 DPWM1_SYNC
_FET_SEL
25-24 DPWM0_SYNC
_FET_SEL
23-20 Reserved
19-18 DPWM3_SYNC
_SEL
17-16 DPWM2_SYNC
_SEL
15-14 DPWM1_SYNC
_SEL
SNIU028A – February 2016 – Revised April 2016
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Figure 5-10. DPWM Mux Register (DPWMMUX)
29 28
DPWM2_SYNC_FET_SEL
R/W-00
21 20
R-0000
13 12
DPWM0_SYNC_SEL
R/W-00
5 4
DPWM1_FILTER_SEL
R/W-001
Type Reset
R/W 00
Selects Ramp source for DPWM3 PWM-B SyncFET soft on/off
0 = Front End 0 Ramp output selected (Default)
1 = Front End 1 Ramp output selected
2 = Front End 2 Ramp output selected
R/W 00
Selects Ramp source for DPWM2 PWM-B SyncFET soft on/off
0 = Front End 0 Ramp output selected (Default)
1 = Front End 1 Ramp output selected
2 = Front End 2 Ramp output selected
R/W 00
Selects Ramp source for DPWM1 PWM-B SyncFET soft on/off
0 = Front End 0 Ramp output selected (Default)
1 = Front End 1 Ramp output selected
2 = Front End 2 Ramp output selected
R/W 00
Selects Ramp source for DPWM0 PWM-B SyncFET soft on/off
0 = Front End 0 Ramp output selected (Default)
1 = Front End 1 Ramp output selected
2 = Front End 2 Ramp output selected
R 0000
R/W 00
Selects Master Sync for DPWM 3 when DPWM 3 configured in slave mode
0 = DPWM 0 Sync (Default)
1 = DPWM 1 Sync
2 = DPWM 2 Sync
3 = DPWM 3 Sync
R/W 00
Selects Master Sync for DPWM 2 when DPWM 2 configured in slave mode
0 = DPWM 0 Sync (Default)
1 = DPWM 1 Sync
2 = DPWM 2 Sync
3 = DPWM 3 Sync
R/W 00
Selects Master Sync for DPWM 1 when DPWM 1 configured in slave mode
0 = DPWM 0 Sync (Default)
1 = DPWM 1 Sync
2 = DPWM 2 Sync
3 = DPWM 3 Sync
Copyright © 2016, Texas Instruments Incorporated
27 26
DPWM1_SYNC_FET_SEL
R/W-00
19 18
DPWM3_SYNC_SEL
R/W-00
11 10
DPWM3_FILTER_SEL
R/W-010
3 2
DPWM0_FILTER_SEL
Description
Loop Mux Registers Reference
25 24
DPWM0_SYNC_FET_SEL
R/W-00
17 16
DPWM2_SYNC_SEL
R/W-00
9 8
DPWM2_
FILTER_SEL
R/W-010
1 0
R/W-000
Loop Mux
203