Using The T16 For A Timer Interrupt - Texas Instruments UCD3138 Technical Reference Manual

Using the T16 for a Timer Interrupt

11.12 Using the T16 for a Timer Interrupt
The C code below should provide an approximate 10 KHz interrupt from the T16:
TimerRegs.T16PWM0CMP0DAT.bit.CMP_DAT = 1587;
TimerRegs.T16PWM0CMPCTRL.bit.CMP0_INT_ENA = 1; //interrupt when counter reset
TimerRegs.T16PWM0CNTCTRL.bit.CMP_RESET_ENA = 1; //enable reset by comp 0
TimerRegs.T16PWM0CNTCTRL.bit.SW_RESET = 1;
In UCD3138 the interrupt flags are not cleared automatically by hardware when the interrupt is serviced.
Therefore the interrupt flag needs to be manually cleared by adding the following statement at the end of
the relevant interrupt service routine.
TimerRegs.T16PWM1CMPCTRL.all
When T16 is used for timer interrupt generation, its PWM output can be used as an independent GPIO
simultaneously. This can be done by using the PWM_OUT_ENA, PWM_OUT_DRV, and PWM_OUT bits
described above, or it can be done using the Global I/O registers described elsewhere in this document.
11.13 Using the T16 for PWM Generation
UCD3138RGC (64-pin version) offers two timer PWM outputs (PWM0 and PWM1), but UCD3138RHA
(40-pin version) offers only one timer PWM0 output. The C code below should provide a 50% PWM at
approximately 10 KHz. Consult the UCD3138 device datasheet for ICLK speeds.
TimerRegs.T16PWM0CMP0DAT.bit.CMP_DAT = 1587;
TimerRegs.T16PWM0CMP1DAT.bit.CMP_DAT = 793; //50%50 duty cycle half of comp 0
TimerRegs.T16PWM0CMPCTRL.bit.PWM_OUT_ACTION0 = 1;//1 is for clear pin
TimerRegs.T16PWM0CMPCTRL.bit.PWM_OUT_ACTION1 = 2;//2 is for clear pin
TimerRegs.T16PWM0CNTCTRL.bit.CMP_RESET_ENA = 1; //enable reset by comp 0
TimerRegs.T16PWM0CMPCTRL.bit.PWM_OUT = 0; //make sure that default is a 0
TimerRegs.T16PWM0CMPCTRL.bit.PWM_OUT_DRV = 1; //put zero into output latch
TimerRegs.T16PWM0CMPCTRL.bit.PWM_OUT_ENA = 1; //enable pin as an output
TimerRegs.T16PWM0CNTCTRL.bit.SW_RESET = 1;
This program uses the Capture 0 block to set the PWM pin high at the end of the previous cycle and s
simultaneously reset the counter. Then the Capture 1 block, which is loaded with a value 50% the size of
Capture 0, clears the PWM pin value halfway through the period.
11.14 WD - Watchdog
The watchdog is the smallest module in the timer. It is primarily designed to assist in recovery in the event
of a firmware or processor fault. The watchdog is not intended for use as a source of a timer interrupt. It
doesn't use the central clock – for reliability it has its own unique clock. This clock has a much higher
variation over temperature and voltage, and from device to device than the clock for the rest of the device.
See the data sheet for each device for the details of the variation.
Unlike the other timers, the counter in the watchdog is invisible, and the compare data values are fixed.
The interrupts occur always when the counter is half full and when it is full.
WDCLK
402
Timer Module Overview
| = 3;
Prescaler Counter
Figure 11-3.
Copyright © 2016, Texas Instruments Incorporated
//value to reset counter
//allow counter to run
//value to reset counter
//allow counter to run
Full
Compare
Half
Compare
SNIU028A – February 2016 – Revised April 2016
www.ti.com
WD_RST
WD_WAKE
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