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Table 16-4. Clock Control Register (CLKCNTL) Register Field Descriptions (continued)
Bit
Field
3
CLKDOUT
2-0
Reserved
SNIU028A – February 2016 – Revised April 2016
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Type
Reset
R/W
0
This pin represents the output value of CLKOUT
0 = CLKOUT driven to logic low in output mode (Default)
1 = CLKOUT driven to logic high in output mode
R
000
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SYS – System Module Registers Reference
Description
Control System Module
509