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Here is a list of the IntraMux modes for DPWMA:
•
0 = DPWMA(n) pass through (default)
•
1 = Edge-gen output, DPWMA(n)
•
2 = DPWNC(n)
•
3 = DPWMB(n) (Crossover)
•
4 = DPWMA(n+1)
•
5 = DPWMB(n+1)
•
6 = DPWMC(n+1)
•
7 = DPWMC(n+2)
•
8 = DPWMC(n+3)
Here is a list of the IntraMux modes for DPWMB:
•
0 = DPWMB(n) pass through (default)
•
1 = Edge-gen output, DPWMB(n)
•
2 = DPWNC(n)
•
3 = DPWMA(n) (Crossover)
•
4 = DPWMA(n+1)
•
5 = DPWMB(n+1)
•
6 = DPWMC(n+1)
•
7 = DPWMC(n+2)
•
8 = DPWMC(n+3)
The DPWM number wraps around just like the Edge Gen unit. For DPWM4, DPWM(n+1) is DPWM0,
DPWM(n+2) is DPWM1, and so on.
Note that the Fault logic affects the Fault module, which is before the Edge Gen and IntraMux units (refer
to
Figure
2-1). The effect of a fault must be calculated taking into account the impact of the Edge Gen and
IntraMux units.
Also the GPIO_A_EN & GPIO_B_EN bits inside the DPWMCTRL1 register affect the signal state before
the IntraMux unit. So if these bits are meant to be used to turn the DPWM output off, the bits in the
original DPWM are supposed to be altered. And not the bits in the DPWM module that the outputs are
redirected through.
2.12 Time Resolution of Various DPWM Registers
Different registers in the DPWM block have different time resolutions. Pulse widths are generally
adjustable in nominal 250 picosecond steps, while period and phase shift are adjustable in 4 nanosecond
steps. The sample trigger is adjustable in 16 nanosecond steps.
Register
Phase Trigger,
Period,
Event1,
Blanking A and B Begin
Blanking A and B End
Minimum Duty Cycle Low
Minimum Duty Cycle High
Counter Preset
Sample Trigger 1 and 2
Event2,3,4
Cycle Adjust A and B
Adaptive Sample
SNIU028A – February 2016 – Revised April 2016
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Table 2-1. DPWM Register Time Resolutions in UCD3138
4 ns.
16 ns
250 ps
250 ps
16 ns
Copyright © 2016, Texas Instruments Incorporated
Time Resolution of Various DPWM Registers
Resolution
Number of Bits
14
12
18
16 (signed)
12 (signed)
Digital Pulse Width Modulator (DPWM)
Bit Alignment
Standard
Standard
Standard
Standard
16 ns LSbit
51
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