Dpwm Cycle Adjust B Register (Dpwmcycadjb); Dpwm Cycle Adjust B Register (Dpwmcycadjb) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

DPWM 0-3 Registers Reference

2.31.13 DPWM Cycle Adjust B Register (DPWMCYCADJB)

Address 00050030 – DPWM 3 Cycle Adjust B Register
Address 00070030 – DPWM 2 Cycle Adjust B Register
Address 000A0030 – DPWM 1 Cycle Adjust B Register
Address 000D0030 – DPWM 0 Cycle Adjust B Register
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-18. DPWM Cycle Adjust B Register (DPWMCYCADJB) Register Field Descriptions
Bit Field
15-0 CYCLE_ADJUST_
B
84
Digital Pulse Width Modulator (DPWM)
Figure 2-29. DPWM Cycle Adjust B Register (DPWMCYCADJB)
CYCLE_ADJUST_B
R/W-0000 0000 0000 0000
Type Reset
R/W 0000
Adjusts the PWM B output signal. 16-bit signed number allows output signal to be
0000
delayed or sped up.
0000
0000
Copyright © 2016, Texas Instruments Incorporated
Description
SNIU028A – February 2016 – Revised April 2016
Submit Documentation Feedback
www.ti.com
0