Texas Instruments UCD3138 Technical Reference Manual page 104

DPWM 0-3 Registers Reference
Table 2-36. DPWM Auto Config Max Register (DPWMAUTOMAX) Register Field Descriptions (continued)
Bit Field
22 CBC_PWM_C_EN R/W
21 Reserved
20 CBC_PWM_AB
_EN
19 CBC_ADV_CNT
_EN
18-17 Reserved
16 MASTER_SYNC
_CNTL_SEL
15-14 Reserved
13 CBC_SYNC_CUR
_LIMIT_EN
12 RESON_MODE
_FIXED_DUTY
_EN
11-7 Reserved
6-4 PWM_MODE
3-2 Reserved
1 CLA_EN
0 Reserved
104
Digital Pulse Width Modulator (DPWM)
Type Reset
0
Configures control of PWM B output in Multi-Output Mode when CLA_ENABLE is
asserted
0 = PWM B pulse width controlled by Filter Calculation (Default)
1 = PWM B pulse width controlled by Event3 and Event4 registers
R 0
R/W 0
Sets if Fault CBC changes output waveform for PWM-A and PWM-B
0 = PWM-A and PWM-B unaffected by Fault CBC (Default)
1 = PWM-A and PWM-B affected by Fault CBC
R/W 0
Selects cycle-by-cycle of operation
Normal Mode
0 = CBC disabled (Default)
1 = CBC enabled
Multi and Resonant Modes
0 = PWM-A and PWM-B operate independently (Default)
1 = PWM-A and PWM-B pulse matching enabled
R 00
R/W 0
Configures master sync location
0 = Master Sync controlled by Phase Trigger Register (Default)
1 = Master Sync controlled by CLA value
R 00
R/W 0
Sets how current limit affects slave sync
0 = Slave sync is unaffected during current limit (Default)
1 = Slave sync is advanced during current limit.
R/W 0
Configures how duty cycle is controlled in Resonance Mode
0 = Resonant mode duty cycle set by Filter duty (Default)
1 = Resonant mode duty cycle set by Auto Switch High Register
R 0000 0
R/W 000
DPWM Mode
0 = Normal Mode (Default)
1 = Resonant Mode
2 = Multi-Output Mode
3 = Triangular Mode
4 = Leading Mode
R 00
R/W 0
CLA Processing Enable
0 = Generate PWM waveforms from PWM Register values (Default)
1 = Enable CLA input
R 0
Copyright © 2016, Texas Instruments Incorporated
Description
SNIU028A – February 2016 – Revised April 2016
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