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16.5.4 Abort Exception Status Register (ABRTESR)
Address FFFFFFE8
The Abort Exception Status Register shows the abort cause.
15
14
ADRABT
MEMABT
R/W-0
R/W-0
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-7. Abort Exception Status Register (ABRTESR) Register Field Descriptions
Bit
Field
15
ADRABT
14
MEMABT
13
PACCVIO
12-0
Reserved
SNIU028A – February 2016 – Revised April 2016
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Figure 16-7. Abort Exception Status Register (ABRTESR)
13
12
PACCVIO
R/W-0
R-0 0000 0000 0000
Type
Reset
R/W
0
is bit represents the illegal address abort. An illegal address access was detected in
user mode. An abort was generated due to an illegal address access from either the
MPU or system
User and privilege modes (read)
0 = No illegal address
1 = Abort caused by an illegal address
User and privilege modes (write)
0 = Clears bit to 0
1 = No effect
R/W
0
This bit represents the memory access abort. This bit indicates an illegal memory
access was detected in user mode. An abort was generated due to the illegal
memory access from either the MPU or system.
User and privilege modes (read)
0 = No illegal memory access
1 = Abort caused by an illegal memory access
User and privilege modes (write)
0 = Clears bit to 0
1 = No effect
R/W
0
This bit represents the peripheral access violation error. This bit indicates a
peripheral access violation error was detected during a peripheral Register access in
user mode. An abort was generated due to a peripheral access violation.
User and privilege modes (read)
0 = No peripheral access violation
1 = Abort caused by a peripheral access violation
User and privilege modes (write)
0 = Clears bit to 0
1 = No effect
R
0 0000
0000
0000
Copyright © 2016, Texas Instruments Incorporated
SYS – System Module Registers Reference
Reserved
R-0 0000 0000 0000
Reserved
Description
8
0
513
Control System Module
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