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2.15.11 Blank Enable
The BLANK_A_EN and BLANK_B_EN bits are used for fault detection. They work with the blanking
registers – See
Section 2.26
cause false Cycle By Cycle (CBC) fault detection.
These bits are not duplicated in the AMS registers.
2.15.12 DPWM Mode
The PWM_MODE bits select the mode for the DPWM. See
sections above for the descriptions of the various modes.
These bits are duplicated in the AMS registers.
2.15.13 DPWM Invert
The PWM_A_INV and PWM_B_INV bits invert the output of the DPWMA and DPWMB pins.
These bits do not affect the DPWM status after device reset however. After reset, all DPWM pins
configured as outputs which are actively driving low.
These bits are not duplicated in the AMS registers.
2.15.14 1.15.14 Filter Enable (CLA_EN)
In the past, the filter was called a Control Law Accelerator, so for historical reasons, the Filter Enable bit is
called CLA_EN. This bit, when set, causes the DPWM to take its input from a Filter. Otherwise, the
DPWM output comes from the DPWM registers only.
This bit is duplicated in the AMS registers.
The filter which controls each DPWM is selected by the DPWMx_FILTER_SEL bit in the DPWMMUX
register in the Loop Mux.
2.15.15 DPWM Enable
The PWM_EN bit, when set enables the DPWM channel. If it is 0 (default), the DPWM outputs are set to
the value in the DPWM Fault Polarity bits
Note that if edge generation is enabled, the bits will be controlled by the edge gen logic. To make the bits
go to the desired values, it will be necessary to clear the EDGE_EN bit in DPWMEDGEGEN.
This bit occurs only in the Control 0 register, not in the AMS registers.
2.16 DPWM Control Register 1
Like DPWMCRTL0, the DPWMCTRL1 register contains a wide assortment of control bits for the DPWM.
2.16.1 Period Counter Preset Enable
The PRESET_EN bit adds flexibility for systems with multiple DPWM modules that have different period
starting times. It can be used to start up all DPWMs simultaneously, even if their periods do not start at
the same times. It can also be used for synchronizing these DPWMs.
Normally, the period counter is reset to zero by three events
1. DPWM ENABLE
2. Sync Received (slave mode enabled)
3. Counter reaches Period Register value
If PRESET_EN is enabled, this changes:
1. DPWM_ENABLE – Period Counter set to preset value
2. Sync Received (slave mode enabled) – Period Counter set to preset value
3. Counter reaches Period Register value – Period counter set to zero
SNIU028A – February 2016 – Revised April 2016
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– to enable blanking for current limit detection. Without blanking, noise may
(Section
2.15.10).
Copyright © 2016, Texas Instruments Incorporated
DPWM Control Register 0 (DPWMCTRL0)
Section 2.31
for the mode numbers, and
Digital Pulse Width Modulator (DPWM)
59
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