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//set 10 bit DAC to 100.25 (0.156640625 Volts)
FeCtrl0Regs.EADCDAC.bit.DAC_DITHER_EN = 1;//enable dither
The DAC can also be controlled by other DACs, by the output of filters, or by the constant power module.
The External DAC Control register in the Loop Mux can be used to select which DAC source is used.
There are several options:
0 = DAC 0 Setpoint Selected
1 = DAC 1 Setpoint Selected
2 = DAC 2 Setpoint Selected
3 = Output of Constant Power Module Selected
4 = Filter 0 Output Selected
5 = Filter 1 Output Selected
6 = Filter 2 Output Selected
LoopMuxRegs.EXTDACCTRL.bit.DAC0_SEL = 5; //control DAC 0 with Filter 1
To enable external DAC Control, it is also necessary to set the enable bit for the specific DAC:
LoopMuxRegs.EXTDACCTRL.bit.EXT_DAC0_EN = 1; //enable external DAC for DAC 0
Filter output is used to control the DAC when two filters are used together, typically in average current
mode control, where the voltage error goes to a voltage loop filter, and the output of the voltage loop filter
controls the DAC for a current loop filter.
The actual value being used for the DAC at any given time can be read from the DAC Status register –
DACSTAT.
dac_value = FeCtrl0Regs.DACSTAT.bit.DAC_VALUE;
3.3
Ramp Module
The Ramp Module is used to control the EADCDAC for ramp up and ramp down of current and voltage. It
is also used to ramp up and down the pulse width of Synchronous Rectifier FET pulses to avoid glitches
when enabling and disabling synchronous rectification. Portions of the Ramp Module are also used for
Prebias handling. The Ramp module is also used for the ramp compensation in peak current mode. The
Ramp module can be used for only one purpose at a time. There are three Ramp modules, one for each
front end, so it is possible to have 3 ramp functions running simultaneously.
3.3.1 DAC Ramp Overview
The Front End Control Module in UCD3138 provides the capability to generate an automated ramp of the
DAC set point through hardware. Firmware has the capability to configure the following parameters of the
ramp:
1. Configurable DAC end value at completion of soft-start or soft-stop ramp
2. Configurable DAC step (8.10 format with 10 fractional bits)
3. Firmware can program number of switching cycles per DAC step (Configurable from 1-128)
4. Configurable number of delay cycles prior to start of ramp (Configurable from 0-65535)
5. Ramp can be initiated by one of the following events: firmware start bit, PMBus Control pin, Ramp
Delay Completion pulse from another Front End Control Module or Ramp Completion pulse from
another Front End Control Module
6. Firmware can configure the DAC Saturation Step Size (if EADC is in saturation at time of DAC update,
hardware will increment/decrement DAC Value by DAC Saturation Step Size).
3.3.2 DAC Ramp Start and End Points
The DAC Ramp start point is taken from the EADC DAC Value Register:
FeCtrl0Regs.EADCDAC.bit.DAC_VALUE = 0; //start ramp at 0
SNIU028A – February 2016 – Revised April 2016
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Ramp Module
119
Front End
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