Memory Fine Base Address Low Register 4-16 (Mfbalrx); Memory Fine Base Address Low Register 4-17 (Mfbalrx) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

DEC – Address Manager Registers Reference

15.2.7 Memory Fine Base Address Low Register 4-16 (MFBALRx)

Address FFFFFE24 – Memory Fine Base Address Low Register 4
Address FFFFFE2C – Memory Fine Base Address Low Register 5
Address FFFFFE34 – Memory Fine Base Address Low Register 6
Address FFFFFE3C – Memory Fine Base Address Low Register 7
Address FFFFFE44 – Memory Fine Base Address Low Register 8
Address FFFFFE4C – Memory Fine Base Address Low Register 9
Address FFFFFE54 – Memory Fine Base Address Low Register 10
Address FFFFFE5C – Memory Fine Base Address Low Register 11
Address FFFFFE64 – Memory Fine Base Address Low Register 12
Address FFFFFE6C – Memory Fine Base Address Low Register 13
Address FFFFFE74 – Memory Fine Base Address Low Register 14
Address FFFFFE7C – Memory Fine Base Address Low Register 15
Address FFFFFE84 – Memory Fine Base Address Low Register 16
Figure 15-11. Memory Fine Base Address Low Register 4-16 (MFBALRx)
15
ADDRESS[15:10]
R/W-000000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-15. Memory Fine Base Address Low Register 4-17 (MFBALRx) Register Field Descriptions
Bit Field
15-10 ADDRESS[15:10]
9 AW
8-2 Reserved
1 RONLY
0 PRIV
480
Memory
10 9
AW
R/W-0
Type Reset
R/W 000000
6 Least Significant Bits of the Base Address. The Base Address sets the 22 most
significant bits of the memory address.
R/W 0
R/W 0 0000
Auto-wait-on-write. When this bit is set, any write operation on this memory select
00
takes two system cycles.
0 = Write operation is not supplemented with an additional cycle (Default)
1 = Write operation takes an additional cycle
R/W 0
Read-only protection. This bit sets read-only protection for the memory selected by
the memory select. An illegal access exception is generated when a write is
attempted to the memory.
0 = Read/write access to memory (Default)
1 = Read accesses to memory only
R/W 0
Privilege mode protection. This bit sets privilege mode protection for the memory
Registration selected by the memory select. An illegal access exception is generated
on any access to memory protected by privilege mode.
0 = User/privilege mode accesses to memory (Default)
1 = Privilege mode accesses to memory only
Copyright © 2016, Texas Instruments Incorporated
8
Reserved
R/W-0 0000 00
Description
SNIU028A – February 2016 – Revised April 2016
www.ti.com
2 1 0
RONLY PRIV
R/W-0 R/W-0
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