Sar Timing Register (Sartiming); Sar Timing Register (Sartiming) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

www.ti.com

3.7.14 SAR Timing Register (SARTIMING)

Address 0x0008_0034 – Front End Control 2 SAR Timing Register
Address 0x000B_0034– Front End Control 1 SAR Timing Register
Address 0x000E_0034 – Front End Control 0 SAR Timing Register
10
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-16. SAR Timing Register (SARTIMING) Register Field Descriptions
Bit Field
10-8 SAR_TIMING
_UPPER
7 Reserved
6-4 SAR_TIMING_MID R/W
3 Reserved
2-0 SAR_TIMING
_LOWER
SNIU028A – February 2016 – Revised April 2016
Submit Documentation Feedback
Figure 3-22. SAR Timing Register (SARTIMING)
SAR_TIMING_UPPER
5 4
SAR_TIMING_MID
R/W-011
Type Reset
R/W 100
Configures timing for Bits 9:8 of DAC setpoint for SAR Algorithm
R 0
011
Configures timing for Bits 7:6 of DAC setpoint for SAR Algorithm
R 0
R/W 010
Configures timing for Bits 5:0 of DAC setpoint for SAR Algorithm
Copyright © 2016, Texas Instruments Incorporated
R/W-100
3 2
Reserved
R-0
Description
Front End Control Registers
8
1 0
SAR_TIMING_LOWER
R/W-010
Front End
139