Master Mode Operation Reference - Texas Instruments UCD3138 Technical Reference Manual

Master Mode Operation Reference

If MAN_SLAVE_ACK is high, EOM does not need to be ACKed. The hardware will accept the address
without an ACK, and set the SLAVE_ADDR_READY bit. This also means that if the STOP signal on the
PMBus is followed quickly by a new address, the firmware may see both the EOM and
SLAVE_ADDR_READY bits set. The firmware must be written to deal with this, first handling the message
that just ended, and then dealing with the message that is starting.
Just taking auto address ACK firmware and enabling manual address ACK is not sufficient.
10.7 Master Mode Operation Reference
The PMBus Interface has the capability to initiate any of the available message protocols used for
communication with connected slave modules. Initiating a message begins with programming the Master
Control Register (Address 0h). Upon programming of this register, the message will begin transmission on
the PMBus once the bus is idle and ready for additional messages.
Note that the default mode of the PMBus interface is Slave mode. To operate in Master Mode, it is
necessary to clear the SLAVE_EN bit and to set the MASTER_EN bit in the PMBCTRL3 register.
Within the bits of the Master Control Register, a number of options are provided that help to configure the
PMBus message. The PMBus Interface includes an optional PEC enable bit (Bit 18). Enabled the
PEC_EN bit forces the PMBus Interface to append a PEC byte onto the end of the message. The
firmware is not required to calculate the PEC value or account for the PEC byte when entering the number
of bytes in the message.
The Byte Count bits (Bits 15-8) within the Master Control Register configures the number of data bytes
within the outgoing message. The firmware is required to program the byte count at the start of each
message. A byte count of zero will result in the transmission of a Quick Command message. The byte
count does not include any command bytes, PEC bytes, address bytes or the block length (found in Block
Write/Read messages). The PMBus Interface in Master Mode automatically terminates a valid message
based on the values programmed in the byte count bits. In cases of a slave NACK, the PMBus Interface
also automatically initiates a stop condition to terminate the message and provides the appropriate alarms
to the firmware through the Status Register.
Inclusion of command bytes in the message initiated by the Master is configured through the CMD_EN
and EXT_CMD bits (Bits 17-16 of the Master Control Register). Enabling CMD_EN forces the PMBus
Interface to include a single command byte in the message. On the first programming of the Transmit Data
Register, bits 7-0 will represent the command byte. When enabling EXT_CMD, support for extended
commands is enabled. Bits 15-0 of the Transmit Data Register, after the first program of the Transmit Data
Register, represent the extended command bytes.
Additional control bits within the Master Control Register enable various message protocols for PMBus
applications. Protocols such as Process Call and Group Command Messages require additional
programming with these bits.
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PMBus Interface/I2C Interface
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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