Power Disable Control Register (Pwrdisctrl); Power Disable Control Register (Pwrdisctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

Miscellaneous Analog Control Registers

9.8.7 Power Disable Control Register (PWRDISCTRL)

Address FFF7F040
PCM_CLK_EN
15 14
FILTER2 FILTER1
_CLK_EN _CLK_EN
R/W-1 R/W-1
7 6
DPWM1 DPWM0
_CLK_EN _CLK_EN
R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-15. Power Disable Control Register (PWRDISCTRL) Register Field Descriptions
Bit Field
17 PCM_CLK_EN
16 CPCC_CLK_EN
15 FILTER2_CLK_EN R/W
14 FILTER1_CLK_EN R/W
13 FILTER0_CLK_EN R/W
12 FE_CTRL2_CLK_
EN
11 FE_CTRL1_CLK_
EN
10 FE_CTRL0_CLK_
EN
9 DPWM3_CLK_EN
8 DPWM2_CLK_EN
7 DPWM1_CLK_EN
342
Advanced Power Management Control Functions
Figure 9-10. Power Disable Control Register (PWRDISCTRL)
17
R/W-1
13 12
FILTER0 FE_CTRL2
_CLK_EN _CLK_EN
R/W-1 R/W-1
5 4
SCI1_CLK_EN SCI0_CLK_EN
R/W-1 R/W-1
Type Reset
R/W 1
Clock Enable for Digital Peak Current Control Module
0 = Disables clocks to Digital Peak Current Control Module
1 = Enables clocks to Digital Peak Current Control Module (Default)
R/W 1
Clock Enable for Constant Power/Constant Current Module
0 = Disables clocks to Constant Power/Constant Current Module
1 = Enables clocks to Constant Power/Constant Current Module (Default)
1
Clock Enable for Filter 2 Module
0 = Disables clocks to Filter 2 Module
1 = Enables clocks to Filter 2 Module (Default)
1
Clock Enable for Filter 1 Module
0 = Disables clocks to Filter 1 Module
1 = Enables clocks to Filter 1 Module (Default)
1
Clock Enable for Filter 0 Module
0 = Disables clocks to Filter 0 Module
1 = Enables clocks to Filter 0 Module (Default)
R/W 1
Clock Enable for Front End Control 2 Module
0 = Disables clocks to Front End Control 2 Module
1 = Enables clocks to Front End Control 2 Module (Default)
R/W 1
Clock Enable for Front End Control 1 Module
0 = Disables clocks to Front End Control 1 Module
1 = Enables clocks to Front End Control 1 Module (Default)
R/W 1
Clock Enable for Front End Control 0 Module
0 = Disables clocks to Front End Control 0 Module
1 = Enables clocks to Front End Control 0 Module (Default)
R/W 1
Clock Enable for DPWM 3 Module
0 = Disables clocks to DPWM 3 Module
1 = Enables clocks to DPWM 3 Module (Default)
R/W 1
Clock Enable for DPWM 2 Module
0 = Disables clocks to DPWM 2 Module
1 = Enables clocks to DPWM 2 Module (Default)
R/W 1
Clock Enable for DPWM 1 Module
0 = Disables clocks to DPWM 1 Module
1 = Enables clocks to DPWM 1 Module (Default)
Copyright © 2016, Texas Instruments Incorporated
CPCC_CLK_EN
R/W-1
11 10
FE_CTRL1 FE_CTRL0
_CLK_EN _CLK_EN
R/W-1 R/W-1
3 2
ADC12_CLK PMBUS_CLK
_EN _EN
R/W-1 R/W-1
Description
SNIU028A – February 2016 – Revised April 2016
www.ti.com
16
9 8
DPWM3 DPWM2
_CLK_EN _CLK_EN
R/W-1 R/W-1
1 0
GIO_CLK_EN TIMER_CLK
_EN
R/W-1 R/W-1
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