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•
SCI_RX1 – see above
•
SYNC – useful for synchronizing and phase matching to FET switching signals from another UCD
11.4 T24 Compare Blocks
The counter is also used by 2 compare blocks. Compare blocks are programmed with a 24 bit value.
When the 24 bit counter matches that value, the compare block is triggered.
These compare blocks are best used when the firmware starts an asynchronous process that needs some
other event to follow at a fixed interval. Add the desired interval to the current counter value, and put the
result into the compare register. When the time elapses, the interrupt will occur, or the TCMP pin will
change.
To load the compare register with a fixed interval:
#define FIXED_INTERVAL 100
.....
TimerRegs.T24CMP0DAT.bit.CMP_DAT = TimerRegs.T24CNTDAT.bit.CNT_DAT + FIXED_INTERVAL;
This technique will even work well if an overflow occurs during the interval. Just like the timer, the result
will overflow and be clipped.
The configuration of the Compare Blocks is relatively straightforward. Refer to
11.5 T24 Interrupts
There are 4 or 5 T24 interrupts, depending on the device. Each one has a separate bit in the CIM –
Central Interrupt Module. This means that each interrupt can have an independent interrupt vector, with no
need to read from the timer module to determine which interrupt has occurred. On the UCD3138128A and
UCD3138A64A, the DTC interrupt is combined with one of the T24 interrupts
Please note that the frequency of T24 interrupts is not adjustable. Therefore T24 may not be used for
generating periodic system tick interruptions.
11.6 T16PWMx - 16 Bit PWM Timers
The UCD3138RGC (64-pin version) has 4 independent 16 bit timers. These are best used for repetitive,
regular interrupts, and for PWM generation, for example for fan drive control.
Depending on the specific device, not all timers will have output pins associated with them. Consult the
device datasheet for specific information.
11.7 T16PWMx Summary
The 16PWMx timers have a 16 bit counter driven by a prescaler, which is driven by ICLK. They have 2
compare units which combine to control one output pin. Each compare unit can generate an interrupt, as
can the counter overflow. All of the interrupts from a specific timer are combined into one before being
sent to the CIM interrupt module. Each timer has its own interrupt bit in the CIM.
SNIU028A – February 2016 – Revised April 2016
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T24 Compare Blocks
Section 11.21
for details.
Timer Module Overview
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