Adc Control Register (Adcctrl); Impedance Roll-Off Due To Crosstalk; Adc12 Control Fsm; Conversion - Texas Instruments UCD3138 Technical Reference Manual

Impedance Roll-Off Due to Crosstalk

8.5 Impedance Roll-Off Due to Crosstalk
Except for the external and internal RC values, the initial charge V0 on the S/H capacitor also affects the
time needed to charge the S/H capacitor to the desired voltage level. If the source impedance is high,
there is a large time constant for the S/H capacitor to discharge. Thus the voltage remaining on the S/H
capacitor will affect the next conversion.
Generally, for UCD3138, several ADC channels are used for different monitoring purposes. When
designing the ADC input circuit, it is highly recommended to avoid high impedance node, because high
impedance node may result in extra impedance roll-offs due to crosstalk.
8.6

ADC12 Control FSM

The ADC12 control Finite State Machine (FSM) module controls the conversion, sequencing and storing of
converted ADC data based on the configuration set by firmware. Conversions are controlled by the FSM
and initiated based on the selected trigger reference. Modes of operation for ADC12 conversion are highly
configurable to suit the desired application.
8.7

Conversion

The ADC conversion is controlled by the ADC12 FSM that provides all the necessary control signals for
the successive approximation register (SAR) ADC operation. The binary search algorithm, sampling time
and bit timing are controlled by the state machine based on firmware configuration. 8 sample and hold
timing configurations are provided to run the ADC12 at various sampling frequencies.
Address 0x00040000
31
23 22
EXT_TRIG EXT_TRIG
_GPIO_VAL _GPIO_DIR
R/W-0 R/W-0
15
ADC_SAMPLING_SEL
R/W-000
7
MAX_CONV
R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
NOTE: Even though the ADC12 sampling frequency is preset to 267 Ksps as default by setting the
ADC_SAMPLINGSEL to zero, in order to achieve the best measurement results it is
recommended to set the sampling rate to 267 Ksps by setting the ADC_SAMPLINGSEL to 6:
AdcRegs.ADCCTRL.bit.ADC_SAMPLINGSEL = 6; // Means: ADC sampling rate is set to 267 KS/s
302
ADC12 Overview
Figure 8-9. ADC Control Register (ADCCTRL)
EXT_TRIG_DLY
R/W-0000 0000
21 20
EXT_TRIG EXT_TRIG_EN
_GPIO_EN
R/W-0 R/W-0
13 12
ADC_SEL_REF
R/W-0
4
Copyright © 2016, Texas Instruments Incorporated
19
EXT_TRIG_SEL
R/W-0000
11 10
ADC_ROUND
R/W-0
3 2
SINGLE SW_START
_SWEEP
R/W-0 R/W-0
SNIU028A – February 2016 – Revised April 2016
www.ti.com
24
16
8
BYPASS_EN
R/W-111
1 0
ADC_INT_EN ADC_EN
R/W-0 R/W-0
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