Ramp Cycle Register (Rampcycle); Ramp Cycle Register (Rampcycle) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

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3.7.3 Ramp Cycle Register (RAMPCYCLE)

Address 0x0008_0008 – Front End Control 2 Ramp Cycle Register
Address 0x000B_0008 – Front End Control 1 Ramp Cycle Register
Address 0x000E_0008 – Front End Control 0 Ramp Cycle Register
23
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-5. Ramp Cycle Register (RAMPCYCLE) Register Field Descriptions
Bit Field
23-8 DELAY_CYCLES
7 Reserved
6-0 SWITCH_CYC
_PER_STEP
SNIU028A – February 2016 – Revised April 2016
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Figure 3-11. Ramp Cycle Register (RAMPCYCLE)
DELAY_CYCLES
R/W-0000 0000 0000 0000
Type Reset
R/W 0000
Configures the number of delay cycles before an initiation of ramp sequence. Each
0000
delay cycle consists of n switching cycles, as specified by
0000
SWITCH_CYC_PER_STEP (Bits 6-0). Number of delay cycles can vary from 0 to
0000
65535
0 = Ramp starts without delay (Default)
1 = Ramp starts after (1*SWITCH_CYC_PER_STEP) switching cycles
2 = Ramp starts after (2*SWITCH_CYC_PER_STEP) switching cycles
.......
65535 = Ramp starts after (65535*SWITCH_CYC_PER_STEP) switching cycles
R 0
R/W 000 0000 Selects number of switching cycles per DAC step. Number of subcycles can vary
from 1 to 128.
0 = 1 switching cycle per step (Default)
1 = 2 subcycles per cycle
2 = 3 subcycles per cycle
.......
127 = 128 subcycles per cycle
Copyright © 2016, Texas Instruments Incorporated
SWITCH_CYC_PER_STEP
R/W-000 0000
Description
Front End Control Registers
8
0
127
Front End