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IDE / DCM Detection Control
CLIM/CBC is also used by the Fault Handler, which is described below. The two mechanisms are
completely independent of each other, except they have the same input signal. The Blanking Registers do
not affect the CLIM/CBC signal which goes to the Fault Handler.
This section will describe the logic in the fault handling portion of the DPWM.
All 4 signals, CLIM/CBC, AB,A, and B can be used as fault signals, and all are used in exactly the same
way, except they shut off different DPWM signals.
As shown, there are 2 enable bits, CBC_FAULT_EN for CLIM/CBC, and ALL_FAULT_EN for the other 3.
Each fault has its own 5 bit counter, with a maximum value set by a dedicated x_MAX_COUNT bit-field.
The fault lines are monitored continuously, but only one event per DPWM period is counted. If the
x_MAX_COUNT value is set to 0, the first fault event will shut off the appropriate DPWM pins. The
maximum number of sequential fault periods is 31, if the x_MAX_COUNT field is loaded with a 0x1f.
The faults must occur sequentially. If any period completes without a fault, the counter will be reset.
The faults handler is much simpler than the CLIM/CBC in the timing generator. They simply latch off either
1 or 2 of the DPWM pins. To restart the DPWM, it is necessary to disable it using either the global enable
register:
void global_enable(void)
{
//Enable DPWM0, DPWM1, DPWM2, DPWM3, FE_CTRL0 AND FE_CTRL1 simultaneously.
LoopMuxRegs.GLBEN.all = 0x30F;
}
void global_disable(void)
{
//Disable DPWM0, DPMW1, DPWM2 and DPWM3 simultaneously.
LoopMuxRegs.GLBEN.all = 0x300;
}
Or the local DPWM enable register:
Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 0;
Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 1;
The DPWMINT register can be used to configure Fault interrupts, as well as other interrupts. It can also
be used to read the status of those interrupts. The interrupt bits are cleared by a read. The
DPWMFLTSTAT register shows the status of the faults. These bits are also clear on read bits.
reference section
for bit mapping of these registers.
If the fault is enabled by the ALL_FAULT_EN bit, and it occurs, the FLT_A, FLT_B, FLT_AB flags will be
set. If the appropriate INT_EN bit is set, the DPWM will send and interrupt to the Central Interrupt Module
(CIM). If the interrupt for that DPWM is enabled in the CIM, then an interrupt will be given to the
processor.
6.9
IDE / DCM Detection Control
In addition to the fault detection and connection described above, there are other registers in the Fault
Mux Registers that control other functions. One of these functions is IDE/DCM detection. IDE stands for
Ideal Diode Emulation. DCM stands for Discontinuous Mode. They are both controlled by the IDECTRL
register in the Fault Mux register set.
Some isolated power topologies simple employ rectification diodes on the secondary side. In Ideal Diode
emulation, FETs are used instead of diodes. They are turned on when the diode would be conducting and
turned off when the diode would be reverse biased. This increases efficiency because the voltage drop
across the FET is lower than the drop across the diode. This is called Synchronous Rectification, so the
FETs are called Sync FETs for short.
In continuous mode, current is always flowing, and the sync FET can be turned on for the entire time
when the primary side is off, except for dead times. This function is served perfectly by the Normal Mode
of the DPWM module. Note that IDE/DCM Detection only works in Normal Mode.
In discontinuous mode, however, current is not flowing continuously, so the sync FET must be turned off
before the end of the period to emulate the diode. Otherwise energy can flow back from the secondary to
the primary.
232
Fault Mux
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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